Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-07-22
2003-09-09
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S149000
Reexamination Certificate
active
06618296
ABSTRACT:
FIELD OF INVENTION
The present invention relates to charge pumps for use in integrated circuits. More particularly, the present invention relates to a charge pump having a circuit for controlling the charging current of the charge pump.
BACKGROUND OF THE INVENTION
The demand for less expensive, and yet more reliable integrated circuit components for use in communication, imaging and high-quality video applications continues to increase rapidly. As a result, integrated circuit manufacturers are requiring improved performance in the voltage supplies and references for such components and devices to meet the design requirements of such emerging applications.
One device utilized for providing a regulated voltage supply is a charge pump circuit. Charge pumps are DC/DC converters that utilize a capacitor instead of an inductor or transformer for energy storage, and are configured for generating positive or negative voltages from the input voltage. Charge pumps can be configured in various manners, including a charge pump voltage doubler circuit, i.e., a charge pump circuit configured for doubling the input voltage, as well as tripler and inverter configurations. These charge pumps can operate to multiply the input voltage by some factor, such as by one-half, two, or three times or any other suitable factor of the input voltage, to generate the desired output voltage. In addition, charge pump circuits can be configured for single phase regulation, with a single charge pump capacitor used to charge current during one phase of operation and discharge current during another phase of operation, or for dual phase regulation, in which two charge pump capacitors are configured to operate during both phases of operation, i.e., one of the capacitors is charging current and the other capacitor is discharging current during each phase of operation.
Charge pumps typically utilize transistors and/or diodes as switching devices to provide current paths for charge transfer. On occasions when the sum of any residual voltages of the charging capacitors in a charging/discharging circuit loop is smaller than the voltage of the power supply, a significantly large amount of transient current tends to flow within the loop. Further, an uncontrolled peak current occurring during charging or discharging of the capacitors is only limited by the “on-resistance” of the switching devices and the equivalent series resistance (ESR) of the capacitors. Moreover, the uncontrolled alternating peak current generally flows out of the positive power supply and into the negative power supply, e.g., into ground, thus causing significantly large electromagnetic interference (EMI) to associated electronic circuits. Still further, the large uncontrolled current also tends to charge the output reservoir capacitor which results in large voltage ripples at the output of the charge pump.
With reference to
FIG. 1
, a charge pump regulator circuit
100
configured for dual phase voltage regulation is illustrated. Charge pump regulator circuit
100
includes a charge pump control circuit
102
comprising four switches S
1
, S
2
, S
3
and S
4
and a first pump capacitor C
PUMP
configured for supplying current to a load device during a first phase, and four switches S
1
′, S
2
′, S
3
′ and S
4
′ and a second pump capacitor C
PUMP′
configured for supplying current to a load device during a second phase. In addition, charge pump circuit
100
comprises a reservoir capacitor C
RES
for maintaining charge to a load device R
LOAD
to facilitate regulation of output voltage V
OUT
. A pass device M
1
is coupled between a supply voltage V
IN
and switches S
1
and S
1
′ for regulating output voltage V
OUT
by controlling the output current, e.g., by controlling the discharging current of first pump capacitor C
PUMP
and second pump capacitor C
PUMP′
. For example, for a discharging current of 5 mA alternating from each of first pump capacitor C
PUMP
and second pump capacitor C
PUMP′
, an average total output current of 5 mA can be realized. As a result of the dual phase regulation, output voltage V
OUT
can be configured to be approximately twice the voltage at a node A, i.e., the voltage at the drain of pass device M
1
. However, the charging currents of first pump capacitor C
PUMP
and second pump capacitor C
PUMP′
are determined only by the difference between a supply voltage V
IN
and the residual voltage of capacitors C
PUMP
and C
PUMP′
, the on-resistance of switches S
2
and S
3
and switches S
2
′ and S
3
′, and the ESR of capacitors C
PUMP
and C
PUMP′
.
Charge pump circuit
100
is typically controlled by a clock having a 50% duty cycle, i.e., a clock having a clock phase-one and phase-two. During clock phase-one, switches S
1
and S
4
are closed to allow current to flow through pass device M
1
, switch S
1
, a pre-charged capacitor C
PUMP
, and switch S
4
to load device R
LOAD
, while switches S
2
and S
3
remain in an “off” condition. Meanwhile, switches S
2
′ and S
3
′ are closed to allow charging current to flow through switches S
2
′ and S
3
′ such that pump capacitor C
PUMP′
is pre-charged to approximately the supply voltage V
IN
, while switches S
1
′ and S
4
′ remain in an “off” condition, i.e., opened. During clock phase-two, switches S
1
′ and S
4
′ are closed to allow current to flow through pass device M
1
, switch S
1
′, charged capacitor C
PUMP′
, and switch S
4
′, to load device R
LOAD
, while switches S
2
′ and S
3
′ are opened. Meanwhile, switches S
2
and S
3
are closed to allow re-charging current to flow through switches S
2
and S
3
such that pump capacitor C
PUMP
is again pre-charged to approximately the supply voltage V
IN
, while switches S
1
and S
4
are opened. The above dual phase operation suitably repeats at a fixed frequency controlled by the clock.
The current through pass device M
1
for regulation of output voltage V
OUT
, i.e., the output or discharging current, is controlled by adjusting the gate voltage V
C
of pass device M
1
. For example, with reference to
FIG. 2
, a voltage regulator circuit
200
comprising a charge pump control circuit
202
and an error amplifier
204
can be configured with a negative feedback control loop to provide an output voltage V
OUT
approximately equal to two times the voltage V
A
at node A, i.e., a voltage 2V
A
. Error amplifier
204
is configured to receive a voltage reference V
REF
and a feedback signal V
FB
through feedback resistor network comprising resistors R
1
and R
2
. Accordingly, error amplifier
204
can control gate voltage V
C
, and thus enabling pass device to facilitate regulation of output voltage V
OUT
through regulation of the voltage V
A
at node A.
However, the recharging or inrush current is only limited by the on-resistance of switches S
2
and S
3
and switches S
2
′ and S
3
′. The selection of the on-resistance for switches S
2
and S
3
and switches S
2
′ and S
3
′ is difficult, in that while switches S
2
and S
3
and switches S
2
′ and S
3
′ generally need to be configured to provide a high enough on-resistance to limit any inrush current, switches S
2
and S
3
and switches S
2
′ and S
3
′ must also be configured to provide a low enough on-resistance to output sufficient current at a low level of supply voltage V
IN
. Due to the concurrent need to provide such a low enough on-resistance, a large inrush of current can occur during the closing of switches S
2
and S
3
and switches S
2
′ and S
3
′, for example up to ten times the average output current, thus resulting in conductive noise within the charge pump circuit
100
.
Moreover, as the supply voltage V
IN
increases from a low level to a high level, the on-resistance of switches S
1
, S
2
, S
3
and S
4
tends to decrease to a very low level due to a higher gate driving voltage. Accordingly, the current flowing through, i.e., the current f
Brady W. James
Le Vu A.
Swayze, Jr. W. Daniel
LandOfFree
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