Charge pump for improving memory cell low VCC performance...

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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C365S226000

Reexamination Certificate

active

06215708

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure and method for operating an array of memory cells. More specifically, the present invention relates to a charge pump for driving word lines of an array of memory cells.
2. Discussion of Related Art
FIG. 1
is a circuit diagram of a conventional dynamic random access memory (DRAM) cell
100
. DRAM cell
100
includes n-channel transistor
101
, capacitor
102
, word line
103
and bit line
104
. In general, data is written to DRAM cell
100
by applying a high voltage to word line
103
, thereby turning on transistor
101
. A voltage representative of a data value is then applied to bit line
104
. In response, capacitor
102
stores a charge representative of the data value. For a logic high voltage, it is desirable for a relatively high voltage to be applied to capacitor
102
. To accomplish this, a boosted word line voltage is applied to word line
103
when accessing DRAM cell
100
. The boosted word line voltage has a value of 1.5 times the V
CC
supply voltage. As a result, the voltage applied to capacitor
102
is approximately equal to the V
CC
supply voltage.
FIG. 2
is a graph showing the variation of the boosted word line voltage V
WL
with respect to variations in the V
CC
supply voltage.
As a general rule, the V
CC
supply voltage is allowed to vary +/−10 percent. Thus, a V
CC
voltage supply having a nominal voltage of 5 Volts can vary from 4.5 volts (V
CCMin
) to 5.5 Volts (V
CCMax
). If the V
CC
supply voltage has a value of 4.5 Volts, the word line voltage is boosted to 6.25 Volts, thereby enabling an adequate voltage to be applied to capacitor
102
. If the V
CC
supply voltage has a value of 5.5 Volts, then the boosted word line voltage has a value of about 8.25 Volts. The gate oxide of transistor
101
must therefore be designed to handle 8.25 Volts during normal operating conditions. As a result, the required thickness of the gate oxide of transistor
101
can be relatively thick. If all of the transistors in the device implementing DRAM cell
100
are designed to have the same gate oxide thickness, then the speed of the device may be slowed down by this thicker gate oxide. Otherwise, multiple gate oxide thicknesses may be required, thereby complicating the process used to fabricate the memory array.
FIG. 3
is a circuit diagram of a static random access memory (SRAM) cell
200
. SRAM cell
200
includes cross coupled n-channel transistors
201
-
202
, n-channel access transistors
203
-
204
, load resistors
205
-
206
, word line
207
and bit lines
208
-
209
. In general, SRAM cell
200
is accessed by applying a high voltage to word line
207
, thereby turning on access transistors
203
-
204
. Voltages representative of a data value are then applied to bit lines
208
-
209
. In response, one of transistors
201
-
202
is turned on and the other one of transistors
201
-
202
is turned off. The word line voltage is then de-asserted low, thereby latching a data value into transistors
201
-
202
. One node stores a logic high voltage V
H
, and the other node stores a logic low voltage V
L
. In some SRAM circuits, the word line voltage is pumped to a voltage equal to V
CC
+1 volt, such that the voltage V
H
is equal to V
CC
+1 Volts−V
tb
, where V
tb
is the back bias voltage applied to access transistor
203
(or
204
). Because V
tb
is typically about 1.5 volts, the voltage V
H
is equal to V
CC
−0.5 Volts.
FIG. 4
is a graph illustrating the variation of the boosted word line voltage V
WL
for variations in the V
CC
supply voltage.
Again, the V
CC
supply voltage can vary +/−10 percent, between 4.5 volts (V
CCMin
) and 5.5 Volts (V
CCMax
) . If the V
CC
supply voltage has a value of 5.5 Volts, then the boosted word line voltage has a value of about 6.5 Volts. The gate oxide of access transistors
203
-
204
must therefore be designed to handle 6.5 volts during normal operating conditions. As a result, the gate oxide of access transistors
203
-
204
must be relatively thick. If all of the transistors in the device implementing SRAM cell
200
are designed to have the same gate oxide thickness, then the speed of the device will be slowed down by this thicker gate oxide. Otherwise, multiple gate oxide thicknesses may be required, thereby complicating the process used to fabricate the memory array.
It would therefore be desirable to have a circuit which boosts the word lines high enough to improve memory access characteristics, but not so high as to require a thick gate oxide.
SUMMARY
Accordingly, the present invention provides a memory circuit that operates in response to a V
CC
supply voltage and a ground voltage. The V
CC
supply voltage varies between a minimum V
CC
supply voltage and a maximum V
CC
supply voltage during normal operating conditions of the memory circuit. The memory circuit includes a memory cell array having a plurality of word lines. The memory cells in the memory cell array can be SRAM, DRAM or read only memory (ROM) cells.
The memory circuit also includes a word line voltage generation circuit that generates a fixed word line voltage. The fixed word line voltage is selectively applied to the word lines of the memory cell array. The word line voltage generation circuit generates the fixed word line voltage for all values of the V
CC
supply voltage between the minimum V
CC
supply voltage and the maximum V
CC
supply voltage.
The fixed word line voltage is referenced to the ground voltage, rather than the V
CC
supply voltage. Because the ground voltage does not vary, the boosted word line voltage of the present invention can be controlled more precisely than prior art boosted word line voltages, which are referenced to the V
CC
supply voltage. This improved control enables the boosted word line voltage to be fixed for the entire range of the V
CC
supply voltage. This improved control also enables the boosted word line voltage to be selected to optimize the operating and design characteristics of the memory circuit. In one embodiment, the fixed word line voltage is set equal to the maximum V
CC
supply voltage. As a result, the access transistors that receive the fixed word line voltage do not need to have thicker gate oxide than the other transistors of the memory circuit. This improves the operating speed of the memory circuit, as well as simplifying the process required to fabricate the memory circuit. In other embodiments, the fixed word line voltage can be set greater than the maximum V
CC
supply voltage.
The fixed word line voltage can be referenced to the ground voltage in various manners. For example, the fixed, word line voltage can be referenced to ground by a band gap reference regulator or by a plurality of series-connected diodes.
The present invention will be more fully understood in view of the following description and drawings.


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