Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2007-09-18
2007-09-18
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S088000, C326S092000, C327S148000, C327S157000
Reexamination Certificate
active
11109299
ABSTRACT:
Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuit36receives a control signal depending on an output of a phase comparison circuit34from a control circuit35, and comprises a first P-channel MOS transistor P1, a second P-channel MOS transistor P2and a third P-channel MOS transistor P3, and a first N-channel MOS transistor N1, a second N-channel MOS transistor N2and a third N-channel MOS transistor N3, and a first current source61, a second current source62, a third current source63and a fourth current source64. The transistor P1is turned on and off by an up-signal of the phase comparison circuit34, and the transistor N1is turned on and off by a down-signal of it, and each of the transistor P2, the transistor P3, the transistor N2and the transistor N3is turned on and off on the basis of the control signal of the control circuit35, an output signal from a VCO control terminal65is input to a VCO8through a low pass filter37while causing current to flow through the charge pump circuit36.
REFERENCES:
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patent: 6759912 (2004-07-01), Yamagishi et al.
patent: 2001/0028694 (2001-10-01), Kushibe
patent: 2000-036741 (2000-02-01), None
A Variable Delay Line PLL for CPU-Coprocessor Synchronization Mark G. Johnson, Member, IEEE, and Edwin L. Hudson, Member IEEE IEEE Journal of Solid-State Circuits, vol. 23. No. 5, Oct. 1988.
Kawago Hiroshi
Otsuka Haruhiko
Jordan and Hamburg LLP
Seiko NPC Corporation
Tran Anh Q.
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