Charge pump circuit for integrated memory devices

Details Charge pump circuit for integrated memory devices Charge pump circuit for integrated memory devices

1999-08-20

2000-12-19

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365149, 327536, G11C 1124

Patent

active

061634875

ABSTRACT:
A charge pump circuit for integrated memory devices includes a plurality of stages cascade connected between an input terminal having a first voltage reference and an output terminal. Each stage includes a boost capacitor and one PMOS transistor functioning as a pass transistor. Each PMOS transistor has conduction terminals connected between the previous stage and the next stage, and a control terminal receiving a drive signal. The pass transistors are driven with a voltage that has a ground value when they are to be turned on, and a voltage equal to the highest of the positive voltages involved when they are to be turned off. The highest of the positive voltages involved is the output from the charge pump.

REFERENCES:
patent: 5815446 (1998-09-01), Tobita
patent: 5943271 (1999-08-01), Fujita

Affiliated with

Also associated with

Rating

Charge pump circuit for integrated memory devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Charge pump circuit for integrated memory devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge pump circuit for integrated memory devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-275930