Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-09-05
2003-07-01
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C331S017000
Reexamination Certificate
active
06586976
ABSTRACT:
BACKGROUND
1. Technical Field of the Invention
The present invention relates to a semiconductor circuit, and more particularly, to a charge pump circuit for improving switching characteristics and reducing leakage current and a phase locked loop having the same.
2. Description of Related Art
A phase locked loop (PLL) comprises a circuit for synchronizing the frequency of an output signal of a voltage controlled oscillator with the frequency of an input signal. PLLs are typically utilized for applications such as signal synchronization and frequency synthesization.
In general, a phase-locked loop comprises a phase detector, a charge pump circuit, a loop filter and a voltage controlled oscillator, which are connected in series. The phase detector monitors the difference in phase between an input signal and an output signal of the voltage controlled oscillator and then outputs either an up control signal or a down control signal to the loop filter based on the detected phase difference.
In particular, the loop filter, which typically comprises a capacitor with a large capacitance, charges the capacitor in response to the up control signal so that the output voltage of the loop filter increases. When the output voltage of the loop filter increases, the frequency of the voltage controlled oscillator increases.
Also, the output voltage of the loop filter decreases when the capacitor discharges in response to the down control signal. The frequency of the voltage controlled oscillator decreases when the output voltage of the loop filter decreases.
In other words, if the up control signal is active (that is, logic ‘high’), the charge pump circuit supplies a charge current having a predetermined magnitude to the capacitor of the loop filter. If the down control signal is active, the charge pump circuit draws a discharge current having the same magnitude from the capacitor of the loop filter. In essence, the charge pump circuit is a circuit for controlling the output voltage of the loop filter.
To remove a dead zone in which the PLL cannot detect a minute phase difference, the up and down control signals become active simultaneously for a short time even in a locked state. At this time, the output voltage of the loop filter is maintained at a constant level (so as to stabilize the output frequency of the voltage controlled oscillator) only if the amount of the charge current flowing to the loop filter is exactly the same as that of the discharge current flowing from the loop filter.
However, if there is a difference in phase between the charge current and the discharge current, spurious signals appear in the spectrum of the output signal of the voltage controlled oscillator. To equalize the charge current and the discharge current of the loop filter, their normal states and switching characteristics responding to the up and down control signals are made to be identical with each other.
Also, if the up and down control signals become inactive, the output impedance of the charge pump circuit approaches infinity. Then, only if the amount of leakage current flowing to/from the loop filter is very little, the output voltage of the loop filter is maintained at a constant level.
FIG. 1
is a circuit diagram illustrating a conventional drain-switched charge pump circuit
10
. Referring to
FIG. 1
, the drain-switched charge pump circuit
10
includes a first reference current source
11
, a first current mirror circuit
15
having PMOS transistors P
1
and P
2
and a first capacitor C
1
, a first switching transistor P
3
responsive to an up control signal UP, a second reference current source
13
, a second current mirror circuit
17
having NMOS transistors N
1
and N
2
and a second capacitor C
2
, and a second switching transistor N
3
responsive to a down control signal DN.
Assume that the PMOS transistors P
1
and P
2
have the same aspect ratio (i.e., the ratio of the width of a channel to the length of the channel) and that the first switching transistor P
3
is turned on, the first reference current up REF (i.e., charge current) flows into the drain of the first switching transistor P
3
. Further, assuming that the NMOS transistors N
1
and N
2
have the same aspect ratio and that the second switching transistor N
3
is turned on, the second reference current I
DN,REF
(i.e., discharge current) flows to ground Vss through the drain of the second switching transistor N
3
.
The moment the first and second switching transistor P
3
and N
3
of the drain-switched charge pump circuit
10
are turned on or turned off, a peak current is generated due to difference in drain-source voltage between the transistors P
2
and N
2
connected in series and the first and second switching transistors P
3
and N
3
. Consequently, at the moment of switching, the matching characteristics of the charge current I
UP,REF
and the discharge current I
DN,REF
are extremely poor.
FIG. 2
is a circuit diagram illustrating a conventional gate-switched charge pump circuit
20
. Referring to
FIG. 2
, the gate-switched charge pump circuit
20
includes a first reference current source
21
, a charge unit
25
having a first capacitor C
3
and PMOS transistors P
21
, P
22
, P
23
, and P
24
, a second reference current source
23
, and a discharge unit
27
having a second capacitor C
4
and NMOS transistors N
21
, N
22
, N
23
and N
24
.
The charge unit
25
includes a charging transistor P
22
, a first switching transistor P
23
for switching the charging transistor P
22
, and a second switching transistor P
24
, which reduces the switching load of the PMOS transistor P
21
and complementarily switches with the first switching transistor P
23
. Thus, in the case of switching with the second switching transistor P
24
, the voltage of the source of the second switching transistor P
24
is not changed.
The discharge unit
27
includes the discharging transistor N
22
, the third switching transistor N
23
for switching the discharging transistor N
22
, and the fourth switching transistor N
24
, which reduces the switching load of the NMOS transistor N
21
and complementarily switches with the third switching transistor N
23
. Thus, in the case of switching with the fourth switching transistor N
24
, the voltage of the drain of the fourth switching transistor N
24
is not changed.
One problem associated with the conventional gate-switched charge pump circuit
20
is that switching transistors P
23
, P
24
, N
23
and N
24
, which generate and respectively respond to an UP control signal, an inverted UP control signal, a DN control signal and an inverted DN control signal, must be realized in the gate switched charge pump circuit
20
.
Moreover, when the switching transistors P
23
and P
24
are switched, there exists a period during which they are simultaneously turned on. Accordingly, electric charge stored in the capacitor C
3
is discharged into power supply voltage Vdd. Similarly, when the transistors N
23
and N
24
are switched, there also exists a period during which they are simultaneously turned on. At this time, electric charge stored in the capacitor C
4
is discharged into the ground voltage Vss.
The source voltage of the switching transistor P
24
and the drain voltage of the switching transistor N
24
are not maintained at a constant level and thus before and after switching, the first reference current I
UP,REF
and the second reference current I
DN,REF
are not exactly mirrored to the charge current and the discharge current, respectively. Thus, the matching characteristics of the charge current and the discharge current are extremely poor.
FIG. 3
is a circuit diagram illustrating a conventional source-switched charge pump circuit
30
. In
FIG. 3
, the source-switched charge pump circuit
30
includes a first reference current source
31
, a first current mirroring circuit consisting of PMOS transistors P
31
and P
32
, a first switching transistor P
33
, a first matching transistor P
34
for matching voltage drops occurring in the first switching transistor P
33
. The circuit
30
further includes a se
Cunningham Terry D.
F. Chau & Associates LLP
Samsung Electronics Co,. Ltd.
Tra Quan
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