Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-10-10
2003-03-25
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S227000, C365S226000, C365S185270, C327S536000, C327S537000, C327S534000, C327S545000, C327S546000
Reexamination Certificate
active
06538930
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly a charge pump circuit for generating a positive or negative voltage on the basis of a power supply potential supplied from an external source, and an operation method of a non-volatile memory using the charge pump circuit.
2. Description of the Prior Art
A power supply supplied from an external source to a semiconductor integrated circuit is typically provided with a simple power supply or two power supplies. However, an electric device such as flash memory which needs a plurality of power supplies requires to generate internally a desirable voltage. A circuit playing such a role is called “charge pump circuit”. The charge pump circuit is comprised of a plurality of capacitors, drivers, and oscillators, and cannot help scaling down the dimension of the power supply voltage to perform a reduced power consumption with development of semiconductor integrated circuits in recent years. Therefor, a charge-up from a low voltage is requisite, which directs to increase the stage number of capacitors and drivers. As the miniaturization of a memory array section advances, it is difficult to miniaturize a power supply unit such as charge pump in the actual state.
FIG. 16
is a circuit diagram showing a conventional charge pump circuit for positive voltage generation, for example, as described in JP-A2000-49299. This is a circuit which generates a positive voltage higher than an external power supply. In the drawing, reference numerals
41
and
42
each designate an inverter, which constitutes a driver
104
;
51
-
53
each designate a diode;
61
-
63
each designate a capacitor;
71
designates a capacitive load provided by an internal circuit, wire resistance, and so on;
101
designates an external power supply which feeds Vdd potential;
102
designates a ground which feeds GND potential;
105
designates an oscillator;
108
designates an NMOS transistor (N-channel MOS transistor); and N
1
-N
4
, N
11
, and N
12
each denote a node.
Here, the external power supply
101
is a power supply to be applied so that a user can utilize a semiconductor integrated circuit. In addition, the diodes
51
-
53
, capacitors
61
-
63
, and drivers
104
are components which are necessary for the charge pump circuit for positive voltage generation; and the oscillator
105
is a circuit which generates a pulse-form input signal necessary to operate the charge pump circuit for positive voltage generation.
The input signal generated from the oscillator
105
is input to the inverter
41
constituting the driver
104
as a clock signal &PHgr; to be inverted, thereby resulting in a clock signal /&PHgr;. This branches at the node N
11
into two signals in which the one signal affects the capacitor
62
and the other signal is input to the next inverter
42
to be inverted, resulting in the reverted clock signal &PHgr;. This affects the capacitors
61
and
63
via the node N
12
.
In addition, the NMOS transistor
108
which connects to the external power supply
101
charges the capacitors
61
-
63
and capacitive load, and serves as a transistor which prevents the electric charge boosted to a positive voltage from flowing into the ground
102
. The capacitive load
71
is comprised of decoders, wells, and the like of a non-volatile memory array, and is a capacitance to be charged by the charge pump circuit. Note that NVth represents a threshold voltage value of the NMOS transistor
108
, while Vth represents a threshold voltage value of each of the diodes
51
-
53
.
The operation will be next described below.
The initial status of the charge pump circuit for positive voltage generation is denoted in FIG.
17
. Here, H level (Enable Signal or ES) to the gate of the NMOS transistor
108
is input to be active state, i.e. ON state, and an electric charge of Vdd−(NVth+3Vth) is charged in the capacitive load
71
. As shown in
FIG. 18
, in the charge-up status, an input signal (INPUT) generated from the oscillator
105
with respect to the aforementioned initial status is input to the driver
104
, the complimentary clock signals &PHgr; and /&PHgr; which are generated via the inverters
41
and
42
constituting the driver
104
are applied alternately to the capacitors
61
-
63
, which are pumped up based on the characteristics of the diodes. In such a way, the output POUT may be booted up to 3Vdd−(NVth+3Vth) at the maximum.
On the other hand,
FIG. 19
is a circuit diagram showing a conventional charge pump circuit for negative voltage generation, which generates a negative voltage of a larger dimension than that of the external power supply
101
. In the drawing, reference numeral
113
designates a PMOS transistor (P-channel MOS transistor); the other components are similar to those of
FIG. 18
, and these redundant description will be omitted. The PMOS transistor
113
fills an electric charge to the capacitors
61
-
63
and capacitive load
71
, while it serves as a transistor in which an electric charge leveled down to a certain negative voltage prevents from flowing into the ground
102
of an external power supply. Note that PVth denotes a threshold voltage value of the PMOS transistor
113
.
In this case, a difference between the charge pump circuits for positive voltage generation and for negative voltage generation is simply in that the polarity of the electric charges to be charged in the capacities
61
-
63
and
71
is contrary; the operation detail from the initial status to the charge-up status is the same, and the description will be omitted. In the charge pump circuit for negative voltage generation, the output NOUT may be leveled down upto a voltage of −3Vdd+(PVth+3Vth) at the maximum.
Then,
FIGS. 20 and 21
are circuit diagrams showing a conventional charge pump circuit, for example, disclosed in JP-A 07/177729;
FIG. 20
represents a positive voltage output status, while
FIG. 21
represents a negative voltage output status. A problem will be described below when both positive and negative voltages are generated by a simple charge pump circuit. In the drawings, reference numeral
64
designates a capacitor;
109
designates a PMOS transistor; and the other components are similar to those of the circuits of
FIGS. 18 and 19
above.
A difference between such a charge pump circuit and the above-described charge pump circuit which can generate only either of positive and negative voltages is as follows: The ground
102
is connected to the node N
4
by way of the PMOS transistor
109
, and the capacitor
64
is prepared instead of the capacitive load
71
, whereby the input signal generated from the oscillator
105
via the driver
104
is provided as clock signals &PHgr; and /&PHgr;.
The operation will be next described below.
Referring to
FIG. 20
, for the purpose of generating a positive voltage, when H level is input to the gate of the NMOS transistor
108
and H level is input to the gate of the PMOS transistor
109
, the NMOS transistor
108
is ON state, while the PMOS transistor
109
is OFF state. Thus, since the charge pump circuit is equivalent to that shown in
FIG. 16
, when the complimentary clock signals &PHgr; and /&PHgr; (Vdd potential) are input to the capacitors
61
-
64
via the inverters
41
and
42
constituting the driver
104
, the potentials of the nodes N
1
-N
4
are leveled up and down in synchronization with the clock signals &PHgr; and /&PHgr; in pulse form, and the capacitors
61
-
64
are pumped up, coupled with the characteristics of the diodes
51
-
53
, thereby providing a positive voltage output POUT.
On the other hand, referring to
FIG. 21
, for the purpose of generating a negative voltage, when L level is input to the gate of the NMOS transistor
108
and L level is input to the gate of the PMOS transistor
109
, the NMOS transistor
108
is OFF state, while the PMOS transistor
109
is ON state. In such a way, since the charge pump circuit is equivalent to that of
FIG. 1
Ishii Motoharu
Omoto Kayoko
Mitsubishi Denki & Kabushiki Kaisha
Tran Andrew Q.
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