Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
1999-12-14
2001-04-03
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S189110, C365S226000, C327S536000
Reexamination Certificate
active
06212107
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a step-up circuit for stepping up an external power supply voltage that is supplied from outside, and particularly to a charge pump circuit that generates a stepped-up voltage that is applied to the word lines of a semiconductor memory device, and to a step-up circuit that is provided with such a charge pump circuit.
2. Description of the Related Art
In recent years, semiconductor integrated circuit devices such as semiconductor memory devices do not only use external power supply voltage V
CC
supplied from outside as is, but rather, in the interest of promoting low power consumption and improving element reliability, step down or step up voltage to generate a prescribed internal power supply voltage which is then supplied to each of the necessary internal circuits.
As a semiconductor integrated circuit device with necessitating this type of internal power supply voltage, DRAM (Dynamic Random Access Memory), for example, typically has a configuration that includes a storage capacitor that stores information by storing a signal charge in a memory cell and a switching transistor for controlling the storage/discharge of the signal charge in the storage capacitor, an n-channel MOS field effect transistor (hereinbelow referred to as a “NMOS transistor”) being used as the switching transistor.
The switching transistor has its drain connected to a bit line, its gate connected to a word line, and its source connected to ground by way of the storage capacitor, and the transistor cannot be turned ON unless a voltage is applied to the gate that is higher than the source voltage by a threshold voltage V
TH
. The source voltage normally varies between 0 and V
CC
, so a voltage of at least (V
CC
+V
TH
) must be applied to the gate to turn ON the switching transistor. A step-up circuit that steps up the external power supply voltage V
CC
generates a stepped-up voltage that is applied to the gate (word line) of the switching transistor.
The voltage endurance of transistors used in semiconductor integrated devices in recent years, however, has tended to decrease with miniaturization. The power supply voltage must consequently be decreased, but in the interest of providing a power supply that is shared with other logic circuits composed of TTL (Transistor-Transistor Logic), a configuration is adopted in which an external power supply voltage V
CC
is stepped down by a step-down power supply circuit provided inside the chip, this stepped-down voltage then being supplied to the necessary internal circuits.
For example, if external power supply voltage V
CC
is made 5 V, the internal power supply voltage that is supplied to internal circuits requiring a stepped-down voltage is stepped down to 3.3 V by a step-down power supply circuit. Despite miniaturization of the transistor size, the threshold voltage V
TH
of transistors is not necessarily scaled down as is the power supply voltage.
In semiconductor integrated circuit devices, burn-in tests are commonly carried out after fabrication to eliminate initial defects. In a burn-in test, a voltage that is higher than the normal external power supply voltage V
CC
is applied to the semiconductor integrated circuit that is under test. In DRAM, the substrate is biased to a negative voltage to improve charge-holding characteristics, and in such a case, a voltage which is the sum of the negative voltage to the substrate added to the step-up voltage is applied to transistors used in the step-up circuit. Breakdown may occur when a voltage that exceeds the junction voltage endurance is applied.
In Japanese Patent Laid-open No. 140889/94 (hereinbelow referred to as “the first example of the prior art”), a semiconductor device is proposed that is provided with a clamping circuit that clamps the stepped-up voltage and a clamping control means for allowing change of this clamped voltage, thereby preventing junction breakdown of transistors within the step-up circuit by changing the clamped voltage used during normal operation and during a burn-in test.
In the semiconductor device described in the first example of the prior art, the step-up circuit is caused to operate only when high voltage is necessary (for example, during memory access), and when high voltage is not necessary, the output of the step-up circuit is connected to a ground potential line by the clamping circuit, whereby the voltage of the stepped-up voltage line for supplying stepped-up voltage to internal circuits is made to equal the ground potential.
Since parasitic capacitance is present in a stepped-up voltage line of this type of configuration, the step-up circuit charges the parasitic capacitance of the stepped-up voltage line each time the memory is accessed, and the electric charge of the parasitic capacitance of the stepped-up voltage lines that has been stored must then be discharged each time access is completed. In particular, stepped-up voltage lines have become longer with the increase in memory capacitance in semiconductor memory devices of recent years, thereby resulting in a trend toward an even greater parasitic capacitance and a consequent increase in the current consumed by a step-up circuit.
In addition, because the charge that has been stored in the parasitic capacitance of the stepped-up voltage lines is discharged by the clamping circuit, the loss current by the clamping circuit results in greater consumption of current by the step-up circuit. The high current consumption of the step-up circuit of the first example of the prior art as described hereinabove necessitates transistors having high current supply capabilities, and a greater loss current therefore flows to the clamping circuit than in the second example of the prior art, to be described hereinbelow.
When accessing memory, the charging of the stepped-up voltage lines when the step-up circuit is first operated lengthens the time for the voltage of the word lines that are connected to the stepped-up voltage lines to reach a prescribed value, and the speed of reading and writing information therefore drops. In order to make the voltage of the stepped-up voltage lines reach the prescribed value in a shorter time, the capacitance of a step-up capacitor should be made greater than the parasitic capacitance of the stepped-up voltage lines. When the capacitance of the capacitor is increased, however, the chip area also increased.
To solve the above-described problem of the first example of the prior art, Japanese Patent Laid-open No. 153493/94 (hereinbelow referred to as the “second example of the prior art) proposes a configuration in which a stepped-up voltage is always outputted and a control circuit turns the connection of the step-up circuit output and word lines ON and OFF.
Since the stepped-up voltage lines are always charged in the configuration of the second example of the prior art, the consumption of power that accompanies the charge and discharge of the stepped-up voltage lines can be suppressed and the rise time of the voltage of the word lines is not delayed. In addition, the chip area is not increased because there is no need to increase the capacitance of the step-up capacitor.
In addition, the provision of a limiting circuit for limiting the stepped-up voltage and a step-up clock voltage control circuit for limiting the output amplitude of a clock driver for driving a step-up clock in the second example of the prior art allows a decrease in the power consumption of the step-up circuit that includes a limiting circuit.
Nevertheless, the use of MOS transistors having drains and gates connected together as a diode for rectifying the step-up clock in the second example of the prior art results in the problems of large voltage drops due to the diode, poor rectifying efficiency, and inability to obtain the desired step-up voltage.
Japanese Patent Laid-open No. 14529/94 (hereinbelow referred to as the “third example of the prior art”) proposes a step-up circuit that improves rectifying efficiency by not connecting transi
McGinn & Gibb PLLC
NEC Corporation
Nguyen Tan T.
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