Charge injector transistor memory

Details Charge injector transistor memory Charge injector transistor memory

1976-03-01

1978-05-16

Konick, Bernard

Static information storage and retrieval

Systems using particular element

Capacitors

365177, 357 43, G11C 1124, G11C 1140

Patent

active

040902544

ABSTRACT:
Disclosed is a dynamic memory cell storing digital information, particularly adapted for integrated semiconductor circuit fabrication. The circuit configuration has a bipolar transistor with information storage preferrably in the capacitance of the junctions, and a field effect transistor (FET) for selectively injecting charge into the capacitances. In integrated form, isolation is required only between columns of cells, a buried subcollector forming a common sense line for the entire column, while each of the base regions (also used as a first controlled region of the FET) requires no external contact at all. A further impurity region formed into each column of cells forms a second region of the FET and can be used as a bit line for the entire column. In one embodiment, separate contacts are provided for each of the emitter regions and each of the FET gate regions, while in another embodiment, only a single contact to both of the emitter region and FET gate region of each cell is required.

REFERENCES:
patent: 3390273 (1968-06-01), Weckler
patent: 3699540 (1972-10-01), Lynes et al.
patent: 3729719 (1973-04-01), Wiedmann
patent: 3827034 (1974-07-01), Colaco
patent: 3949243 (1976-04-01), Sander et al.

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