Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-01-16
2003-05-20
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185220, C365S185290
Reexamination Certificate
active
06567303
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to memory systems and in particular to a system and method for programming and erasing sectors of bits in an electronic flash memory device having dual bit memory transistor cells using virtual ground architecture.
BACKGROUND OF THE INVENTION
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in place, flash memory is less expensive and more dense. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bit line. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a single column is connected to the same bit line. In addition, each flash cell has its stacked gate terminal connected to a different word line, while all the flash cells in the array have their source terminals connected to a common source terminal. In operation, individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Such a single bit stacked gate flash memory cell is programmed by applying a voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomena called “Fowler-Nordheim” tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage (VT) of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, an electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
In conventional single bit flash memory devices, an erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells, which fail the initial verification. Thereafter, the erased status of the cell is again verified, and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
Recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell. The conventional programming and erase verification methods employed with single bit stacked gate architectures are not adequate for such dual bit devices. Recently, dual bit flash memory structures have been introduced that do not utilize a floating polysilicon gate, such as an ONO flash memory device that employs a polysilicon layer over the ONO layer for providing wordline connections. Conventional techniques do not address the characteristics associated with these types of devices. Therefore, there is an unmet need in the art for new and improved programming and erase methods and systems, which ensure proper programming and erasure of data bits in a dual bit memory virtual ground architecture, and which account for the structural characteristics thereof.
SUMMARY OF THE INVENTION
A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.
The present invention allows for efficient and thorough programming, erasure and verification, which minimizes data retention and over-erase issues similar to those caused in an ONO dual bit cell architecture. The invention provides significant advantages when employed in association with dual bit memory cells formed from an ONO architecture. However, it will be recognized that the invention finds utility in association with dual bit memory cell architectures generally, and that the invention is thus not limited to any particular dual bit cell usage implementation or configuration. Although, charge associated with programming of a single bit in the dual bit memory cell is isolated, it causes the associated cell to program harder making it more difficult to erase. For example, residual charge can be accumulated into the central region of the cell, which cannot be erased by a normal erasure of the bit by itself. Therefore, the system and methodology includes programming, verifying and erasure of both a normal bit and a complimentary bit of the cell, which are opposite sides of the same ONO transistor. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the transistor followed by a single sided erase pulse to one side and a single sided erase pulse to the other side.
In one aspect of the
Derhacobian Narbeh
Hamilton Darlene G.
Han Michael K.
Thurgate Tim
Wang Janet S. Y.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Phan Trong
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