Charge gain/charge loss junction leakage prevention for...

Details Charge gain/charge loss junction leakage prevention for... Charge gain/charge loss junction leakage prevention for...

2000-01-18

2002-10-15

Dang, Trung (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S320000, C438S257000, C438S258000

Reexamination Certificate

active

06465835

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to nonvolatile memory devices. Even more particularly, the present invention relates to flash memory utilizing periphery and core stacks.
BACKGROUND OF THE INVENTION
Memory devices such as flash memory or electrically erasable programmable read only memory (EEPROM) are known. U.S. Pat. No. 5,656,513 to Wang et al. and U.S. Pat. No. 5,693,972 to Liu disclose prior art flash memory devices.
FIG. 1
is a cross sectional view of an incomplete flash memory structure
10
, known in the prior art. Shown as parts of the flash memory structure
10
are a substrate
12
, a plurality of core stacks
16
mounted on the substrate
12
in a row forming a word line, and a periphery stack
14
associated with the word line of the core stacks mounted on the substrate
12
spaced apart from the core stacks
16
.
A first oxide layer
18
forms a first layer of the periphery stack
14
and the core stacks
16
, where the first oxide layer
18
has a first side adjacent to the substrate
12
and a second side opposite from the first side. The first oxide layer
18
for the periphery stack
14
is a gate oxide layer, and the first oxide layer
18
for the plurality of core stacks
16
are tunnel oxide layers. A first polysilicon layer
20
forms a second layer of the core stacks
16
, where the first polysilicon layer
20
has a first side adjacent to the second side of the first oxide layer
18
and a second side opposite from the first side of the first polysilicon layer
20
. An interpoly dielectric layer
22
forms a third layer of the core stacks
16
, where the interpoly dielectric layer
22
has a first side adjacent to the second side of the first polysilicon layer
20
and a second side opposite from the first side of the interpoly dielectric layer
22
. A second polysilicon layer
24
forms a second layer of the periphery stack
14
and a fourth layer of the core stacks
16
. A silicide layer
26
forms a third layer for the periphery stack
14
and a fifth layer for the core stacks
16
. A third polysilicon layer
28
forms a fourth layer of the periphery stack
14
and a sixth layer of the core stacks
16
. An antireflective coating (ARC)
29
forms a fifth layer of the periphery stack
14
and a seventh layer of the core stacks
16
.
A protective oxide layer
31
is placed over the periphery stack
14
, the core stacks
16
and the uncovered Surface of the substrate
12
, as shown in
FIG. 2. A
first high temperature oxidation oxide (HTO) layer
32
is placed over the protective oxide layer
31
. A first resist mask
34
is placed over parts of the first HTO layer
32
to cover the periphery stack
14
and parts of the core stacks
16
and the drain area.
The parts of the first HTO layer
32
not covered by the first resist mask
34
are etched partially away to create self aligned source spacers
36
, as shown in FIG.
3
. The flash memory structure
10
is subjected to a deep source implant to form deep source regions
37
for the core stacks in the substrate
12
. The first resist mask
34
is then stripped away and a second HTO layer
39
is placed over the first HTO layer
32
, self aligned source spacers
36
, and the uncovered parts of the core stacks
16
and substrate
12
surface, as shown in FIG.
4
.
The second HTO layer
39
is etched away to form source/drain spacers
40
, as shown in FIG.
5
. The flash memory structure is subjected to a shallow dopant implant to create shallow more highly concentrated drain regions
42
and source regions
43
. A third HTO layer
45
is placed over the self aligned source and source/drain spacers
36
,
40
, and the uncovered parts of the core stacks
16
, periphery stack
14
and substrate
12
surface. An intermetallic dielectric layer (IDL)
46
is placed over the third HTO layer
45
. A trench is etched into the intermetallic dielectric layer (IDL)
46
and is filled to create a tungsten plug
48
electrically connected to a drain region
42
of a core stack
16
.
Problems in the manufacture of flash memory according to the above mentioned process may occur, because etching after the core stacks
16
have been formed may damage the core stacks
16
. In addition, process induced charging, caused by processes such as plasma deposition, etching, and chemical mechanical polishing, creates ions which may damage the core stacks
16
by way of trapped charges moving between the tungsten plug
48
and the core stacks through the source/drain spacers
40
.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention involves producing a flash memory device on a substrate by: forming a plurality of core stacks on the substrate; forming at least one periphery stack on the substrate; forming an oxide layer on the core stacks the periphery stack and the substrate; applying a protective layer over the oxide layer, etching back the oxide layer and protective layer to form side walls around the periphery and core stacks, applying a first HTO layer over the side walls, etching back the first HTO layer to form self aligned source spacers doping the uncovered substrate, applying a second HTO layer, etching back the first and second HTO layers to form source/drain spacers, and doping the uncovered substrate, and then applying an HTO layer over the spacers, periphery stack, core stacks and substrate.
Advantages of the present invention include, but are not limited to, providing a flash memory device with reduced damage to the core stacks and reduced current leakage between the plugs and the stacks. Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION.”


REFERENCES:
patent: 5614748 (1997-03-01), Nakajima et al.
patent: 5656522 (1997-08-01), Komori et al.
patent: 5793673 (1998-08-01), Pio et al.
patent: 6248627 (2001-06-01), Pham et al.

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