Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
1999-09-24
2001-04-17
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S214000, C257S215000, C257S248000, C257S252000
Reexamination Certificate
active
06218686
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and manufacturing methods therefor, and more particularly, to charge coupled devices which enable charge transfer and manufacturing methods therefor.
BACKGROUND OF THE INVENTION
Charge coupled devices are dynamic charge transfer devices which transfer charge via a predetermined path according to clock pulses applied to a gate electrode. A charge coupled device may be constituted of metal oxide semiconductor (MOS) transistors which are connected in series to one another via their gates.
Charge coupled devices are widely used as imaging devices, whereby the charge coupled device is combined in parallel to a group of photo-diodes to form a device capable of sensing optical signals. Charge coupled devices are also used in various analog and digital signal processing applications.
Early charge coupled devices, such as the one suggested by Bell and Smith in 1969, comprised an insulation layer and gate electrodes arranged to constitute a MOS capacitor on a semiconductor substrate. However, the simple planar arrangement of the gate electrodes on this device made it difficult to control the shapes of the potential wells under the gate electrodes. Therefore, devices have been suggested in which the gate electrodes are isolated from one another while being partially overlapped with each other. Of these devices, the structure which has gained the widest acceptance has a plurality of gate electrodes formed on a semiconductor substrate with insulation layers formed therebetween, and charge transfer areas formed under the gate electrodes.
Charge-coupled devices are divided into a pseudo 2-phase charge coupled device, 3-phase charge coupled devices, and 4-phase charge coupled devices according to their driving method, and the structural configurations of the charge coupled devices are modified in accordance with their driving methods. The pseudo 2-phase charge coupled device uses simple driving pulses, despite its low capacity of charge transfer as compared with other configurations, thus it is widely used as a horizontal charge transfer device of a charge coupled device-type image device requiring high speed operation.
FIG. 1
is a sectional view of a conventional pseudo 2-phase charge coupled device. In
FIG. 1
, reference numeral
10
denotes a semiconductor substrate, reference numeral
12
denotes a buried channel for a buried charge coupled device, and reference numeral
20
denotes an interlayer insulation layer. As illustrated in
FIG. 1
, such a conventional charge coupled device has first gate electrodes
16
spaced from one another by a predetermined distance, second gate electrodes
18
positioned between the first gate electrodes
16
, and potential areas
14
formed under the second gate electrodes
18
. A first clock terminal &phgr;1 is connected to a first gate electrode
16
and a second gate electrode
18
to form a unit transfer group, and a second clock terminal &phgr;2 is connected to a first gate electrode
16
and a second gate electrode
18
to form another unit transfer group. Mutually opposite clock signals are applied to the first and second clock terminals &phgr;1 and &phgr;2.
The potential areas
14
are formed by ion implantation using the first gate electrodes
16
as a mask, and thus potential areas
14
are aligned with the first gate electrodes
16
. These potential areas
14
form potential wells in a charge transferring direction.
The migration of charge of the charge coupled device of
FIG. 1
is illustrated in the potential distribution diagram of FIG.
2
. Referring to
FIG. 2
, charge stored in a potential well in the left side of the figure migrates to the right when a clock pulse is applied to the first and second clock terminals &phgr;1 and &phgr;2. The arrow in
FIG. 2
indicates the direction of charge transfer.
In many applications, such as high speed horizontal charge coupled devices of a charge coupled device-type image device, it is desirable to form as many transfer groups as possible in an area of a given unit length. However, as the pseudo 2-phase charge coupled device of
FIG. 1
applies a single clock pulse to two gate electrodes, limitations in the resolution achievable during photolithography place a limit on the minimum length of the charge transfer groups. Such limits emerge as a serious problem in applications requiring a large number of charge transfer groups per unit area.
To avoid the above-mentioned problem, a device has been suggested in which a single gate electrode is used as a unit transfer group by forming a potential area below only half the area of each gate electrode. Such a device is illustrated in FIG.
3
.
The charge coupled device depicted in
FIG. 3
is identical to the charge coupled device depicted in
FIG. 1
in terms of the arrangement of the first and second gate electrodes
16
and
18
. However, a potential area is
15
formed under each of the first and second gate electrodes
16
and
18
, and each of the clock terminals &phgr;1 and &phgr;2 are connected to only a single gate electrode. Through these modifications, the size of the area reserved for the charge coupled device of
FIG. 3
can be reduced to at least half of the area of the charge coupled device of FIG.
1
. Thus, if the sizes of horizontal charge transfer devices of a charge coupled device-type image device are comparable, the device of
FIG. 3
can include twice as many charge transfer groups as the device of FIG.
1
.
In fabricating the charge coupled device of
FIG. 3
, the potential area
15
, may be formed via ion implantation after an ion implantation mask is formed using photolithography. However, when such a method is used, it may be difficult to align each potential area
15
with each of the gate electrodes
16
and
18
. Thus, in the charge coupled devices of
FIG. 3
, there is a likelihood that an unnecessary local potential barrier or well is created due to the misalignment of a potential area and a gate electrode at a gate electrode boundary, thereby lowering charge transfer efficiency.
U.S. Pat. No. 4,097,885 discloses another charge coupled device having a gate structure that utilizes three depositions of electrically conductive material to form electrodes. This patent indicates that via such a technique a two-phase charge coupled device may be fabricated that occupies less wafer surface area and operates at faster speeds than conventional charge coupled devices.
SUMMARY OF THE INVENTION
In light of the aforementioned limitations with conventional charge coupled devices, it is an object of the present invention to provide a charge coupled device which provides higher charge transfer efficiency.
It is a second object of the present invention to provide a charge coupled device where the area occupied by a unit transfer group is reduced.
Yet another object of the present invention is to provide a method for manufacturing such a charge coupled device.
The above-stated objectives are provided by a charge coupled device which includes a transfer electrode portion having a first gate electrode, a second gate electrode which has an end portion that partially overlaps an end portion of the first gate electrode, and a third gate electrode which has one end portion partially overlapping the other end portion of the first gate electrode and the other end portion thereof partially overlapping the other end portion of the second gate electrode. This charge coupled device further includes a charge transfer portion located in a semiconductor substrate under the first, second and third gate electrodes. The charge transfer portion has a first potential area partially formed in the semiconductor substrate under the second gate electrode and a second potential area formed in the semiconductor substrate under the third gate electrode. This charge coupled device also includes a clock portion comprising a first clock terminal that is simultaneously connected to both the first and third gate electrodes, and a second clock terminal that is connected to the second gate electrode
Fenty Jesse A.
Lee Eddie C.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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