Charge coupled device memory system with burst mode

Details Charge coupled device memory system with burst mode Charge coupled device memory system with burst mode

1975-05-01

1978-04-11

Curtis, Marshall M.

Static information storage and retrieval

Read/write circuit

Data refresh

365 78, 365 73, 364900, G11C 700

Patent

active

040841545

ABSTRACT:
A circular shift register memory system comprising L sections each having K circular charge storage shift registers of N bits each for storing blocks of N, K-bit words and accessing the words or blocks thereof in parallel. The L memory sections are refreshed by N-bit clock bursts which are successively and periodically applied to the memory sections by a refresh counter, decoder and gating logic. A read/write decoder decodes memory section addresses and controls the application of N-bit clock bursts to the particular addressed memory sections for access purposes. In a random access mode, word access is facilitated by counters which count the number of read/write or refresh clock pulses for comparison to a word address. A memory section comparator prevents interference between access and refresh operations by inhibiting the refresh circuitry if the refresh counter directs refresh of a memory section undergoing access and by inhibiting the read/write circuitry in certain cases where access is requested to a memory section undergoing refresh.

REFERENCES:
patent: 3748651 (1973-07-01), Mesnik
patent: 3760379 (1973-09-01), Nibby, Jr. et al.
patent: 3859640 (1975-01-01), Eberlein et al.
Capacitor Storage Ring, Callahan; I.B.M. Tech. Discl. Bull.; p. 17; vol. 2, No. 3; Oct. 1959.

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