Charge booster for CMOS dynamic circuits

Details Charge booster for CMOS dynamic circuits Charge booster for CMOS dynamic circuits

2000-01-07

2002-06-18

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S093000, C327S208000

Reexamination Certificate

active

06407584

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to logic circuits and in particular to dynamic logic circuits. Still more particularly, the present invention relates to a charge booster for maintaining a charge level at a node of a dynamic logic circuit and a method of operation thereof.
2. Description of the Related Art
Integrated complementary metal-oxide-semiconductor (CMOS) logic circuits typically come in two types; static and dynamic field effect transistor (FET) logic gates. A static logic gate generally does not require an external clock signal to control its operation. Furthermore, the static logic gate can maintain its state for as long as a supply voltage is applied to it. A dynamic logic gate, on the other hand, generally does not hold its state indefinitely and requires an external clock signal to operate the circuit, i.e., in a precharge and evaluation mode. Dynamic CMOS logic gates, in contrast to static gates, generally tend to yield better performance, consume less power and typically require less silicon area for fabrication.
Charge sharing is a common problem encountered in dynamic logic circuits that may result in a complete system failure. To illustrate the problem, consider the conventional dynamic circuit that is depicted in FIG.
1
.
FIG. 1
illustrates a schematic diagram of a logic circuit that implements a logic function Output=A(B+C+D+E), where input A to an n-channel field effect transistor (NFET) is the dominant input. During the evaluation phase of the dynamic circuit, one or more of the inputs B, C, D and E may go logic high while, at the same time, input A remains at a logic low. This will result in charge at a node, designated precharge, to be shared with a second node, designated INT
1
. The charge sharing between nodes precharge and INT
1
may cause a voltage. drop at the precharge node that, in turn, may cause a voltage rise at the output. This voltage rise, or noise spike, may cause errors in succeeding circuits, or if the charge sharing is significant enough, the logic circuit may even change state erroneously.
A common solution, illustrated in
FIG. 2
, to mitigate the charge sharing problem described above is to drive the voltage at node INT
1
all the way up to a supply voltage level, thus precluding a voltage drop across the nodes precharge and INT
1
.
FIG. 2
illustrates the conventional dynamic logic circuit depicted in
FIG. 1
employing a transistor Pi coupled to the node INT
1
. The operation of transistor P
1
is controlled by using the clock signal as a control signal to selectively turn transistor P
1
ON or OFF. Transistor P
1
has been included in the dynamic logic circuit to charge node INT
1
to a supply voltage level during the precharge phase. In the event that one of the inputs B, C, D or E goes high while input A remains low, there will be no charge sharing since both nodes, i.e., precharge and INT
1
, are at substantially the same voltage level. Since no charge sharing occurs, there is no voltage drop on node precharge and consequently, no voltage rise at the output of the dynamic logic circuit.
The conventional solution discussed above to eliminate the charge sharing problem encountered in dynamic logic however, wastes power. Since transistor P
1
is always turned ON at the precharge phase, node INT
1
is always pulled up to the supply voltage and charged even if none of the inputs B, C, D or E is high. In the case where inputs B, C, D and E are low and input A is high, the charge placed on node INT
1
by transistor P
1
is removed during the evaluation phase. If this set of input conditions is present over multiple consecutive cycles, node INT
1
will be constantly charged and discharged every cycle, resulting in wasted power dissipation. Furthermore, when the dynamic logic circuit is implemented using silicon-on-insulator technologies, the conventional solution illustrated in
FIG. 2
results in bipolar leakage current problems. For example, under the same input conditions as discussed above, i.e., A is high and B, C, D and E are low, the charging of node INT
1
causes the bodies of transistors N
10
through N
13
to be charged high every cycle. This maximizes the parasitic bipolar leakage currents that occur in transistors N
10
through N
13
when node INT
1
is eventually pulled low. These bipolar leakage currents, in turn, may cause the charge at node precharge to drop, resulting in a complete circuit failure.
Accordingly, what is needed in the art is an improved dynamic logic circuit that mitigates the above-described limitations.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved dynamic logic circuit.
It is another object of the present invention to provide a charge booster and a method of operation thereof.
To achieve the foregoing objects, and in accordance with the invention as embodied and broadly described herein, a charge booster is disclosed for a node in a dynamic logic circuit having a logic function evaluation network that includes a switching network and a dominant input switching device that are adapted to receive a plurality of input signals. In one aspect of the present invention, a precharge transistor is first turned on by a clock signal during a precharge phase to precharge the node that is coupled to an output of the dynamic logic circuit. Concurrently, during the precharge phase, an evaluate transistor, operating in a complementary fashion with the precharge transistor, is turned off. Next, during an evaluate phase, the evaluate transistor is turned on by the control signal, i.e., clock signal, permitting the logic function evaluation network to perform the predefined logic function in accordance with the input signals received by the logic function evaluation network. The logic function evaluation network selectively charges or discharges the node to a voltage level based on the predefined logic function. The charge booster includes a charge booster switching device that is coupled to the node in the dynamic logic circuit. The charge. booster switching device, in turn, is controlled by an input to the dominant input switching device. In a related embodiment, the dynamic logic circuit is embodied in an integrated circuit (IC) utilizing Silicon-on-Insulator (SOI) technology. another embodiment of the present invention, the transistors in the switching network and the dominant input switching device are n-channel field effect transistors (NFETS). In this case, the charge booster switching device is a p-channel field effect transistor (PFET). Alternatively, in another advantageous embodiment, the transistors in the switching network and the dominant input switching device are p-channel field effect transistors (PFETs). It should be readily apparent to those. skilled in the art that, in this case, the charge booster switching device will be a n-channel field effect transistor (NFET).
The foregoing description has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.


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patent: 5440243 (1995-08-01), Lyon
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patent: 6094071 (2000-07-01), Ciraula et al.
patent: 6111434 (2000-08-01), Ciraula et al.
patent: 6150869 (2000-11-01), Storino et al.

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