Charge balance techniques for power devices

Details Charge balance techniques for power devices Charge balance techniques for power devices

2011-05-03

2011-05-03

Cao, Phat X (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S341000, C257SE27096

Reexamination Certificate

active

07936013

ABSTRACT:
A vertically-conducting charge balance semiconductor power device includes an active area comprising a plurality of cells capable of conducting current along a vertical dimension when biased in a conducting state, and a non-active perimeter region surrounding the active area. No current flows along the vertical dimension through the non-active perimeter region when the plurality of cells is biased in the conducting state. Strips of p pillars and strips of n pillars are arranged in an alternating manner. The strips of p pillars have a depth extending along the vertical dimension, a width, and a length. The strips of p and n pillars extend through both the active area and the non-active perimeter region along a length of a die that contains the semiconductor power device. The length of the die extends parallel to the length of the strips of p pillars. Each of the strips of p pillars includes a plurality of discontinuities forming portions of a plurality of strips of n regions. The plurality of strips of n regions extends in the non-active perimeter region perpendicular to the length of the die.

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