Charge amplifying trench memory cell

Static information storage and retrieval – Read/write circuit

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

365174, 365149, G11C 700

Patent

active

049706896

ABSTRACT:
A gain memory cell circuit includes a storage capacitor connected between a storage node and ground, a write word line, a read word line, a second capacitor capactively coupling the read word line to the storage node, a read transistor having its source/drain path coupled between the bit line and ground and having its gate coupled to the storage node, and a write transistor having its source/drain path coupled between the storage node and bit line and a control electrode connected to the write word line.

REFERENCES:
patent: 3385729 (1968-05-01), Larchian
patent: 3513365 (1968-06-01), Levi
patent: 3582909 (1971-06-01), Booher
patent: 3614749 (1971-10-01), Radcliffe, Jr.
patent: 3634825 (1972-01-01), Levi
patent: 3691537 (1972-09-01), Burgess et al.
patent: 3699539 (1972-10-01), Spence
patent: 3701980 (1972-10-01), Mundy
patent: 3706891 (1972-12-01), Donofrio et al.
patent: 3878404 (1975-04-01), Walther
patent: 3882472 (1975-05-01), Smith
patent: 4021788 (1977-05-01), Marr
patent: 4168536 (1979-09-01), Joshi et al.
patent: 4462040 (1984-07-01), Ho et al.
patent: 4467450 (1984-08-01), Kuo
patent: 4511911 (1985-04-01), Kenney
patent: 4547793 (1985-10-01), Bergeron
patent: 4549927 (1985-10-01), Goth et al.
patent: 4561172 (1985-12-01), Slawinski et al.
Mashiko et al., "A 4-Mbit DRAM with Folded-Bit-Line . . . ", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, 1987, pp. 643-650.
D. M. Kenney, "Self-Aligned U-Groove Gates . . . ", IBM Technical Disclosure Bulletin, vol. 22, No. 10, 1980, pp. 4448-4449.
K. Terada et al., "A New VLSI Memory Cell Using Capacitance Coupling (CC Cell)", IEEE Trans. Electron Devices, vol. E0-31, No. 9, 1984, pp. 1319-1324.
Terada et al., "Advanced DMOS Memory Cell Using a New Isolation Structure", IEEE Transacitons on Electron Devices, vol. ED-31, No. 9, 1984, pp. 1301-1308.
Jambotkar, "Compact One-Device Dynamic RAM Cell with High Storage Capacitance", IBM Technical Disclosure Bulletin, vol. 27, No. 2, 1984 pp. 1313-1320.
Kenney, "V-Groove Dynamic Memory Cells", IBM Technical Disclosure Bulletin, vol. 23, No. 3, 1980, pp. 967-969.
Leiss et al., "dRAM Design Using the Taper-Isolate Dynamic RAM Cell", IEEE Transactions on Electron Devices, vol. ED-29, No. 4, 1982, pp. 707-714.
Terada et al., "A New VLSI Memory Cell Using MOS Technology (DMOS Cell)", IEEE Transactions on Electron Devices, vol. ED-29, No. 8, 1982, pp. 1301-1308.
Eldin et al., "A Novel JCMOS Dynamic RAM Cell for VLSI Memories", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 3, pp. 715-723.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Charge amplifying trench memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Charge amplifying trench memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge amplifying trench memory cell will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-781777

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.