Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Layout generation
Reexamination Certificate
2008-10-29
2011-11-08
Whitmore, Stacy (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Layout generation
C716S030000, C716S051000, C716S053000, C382S144000, C382S145000
Reexamination Certificate
active
08056027
ABSTRACT:
A method for characterizing thermomechanical properties of an organic substrate includes the steps of: receiving an image of the substrate, the image including a geometric description of the circuit layers of the substrate; selecting a given one of the circuit layers for processing; converting the image to a 2-D FEM image of the given circuit layer; repeating the steps of selecting a given one of the circuit layers and converting the image to a 2-D FEM image of the selected layer until all of the layers have been processed; combining all of the 2-D FEM images corresponding to the layers to form a 3-D FEM image representing at least a portion of the substrate; determining a coefficient of thermal expansion (CTE), modulus and/or Poisson's ratio of the 3-D FEM image; and constructing a 3-D representation of the substrate as a function of the CTE, modulus and/or Poisson's ratio of the 3-D FEM image.
REFERENCES:
patent: 2009/0310848 (2009-12-01), Dang et al.
Zhang, Z. et al., FEM modleing of temperature distribution of a flip-chip no-flow underfill package during solder reflow process, Jan. 2004, IEEE, pp. 86-93.
Yao, Q. et al., “Three-dimensional vs. two-dimensional finite element modeling of flip chip packages”, Dec. 1998., Georgia Institute of Technology. pp. 1-38.
Dang Hien Phu
Khanna Vijaveshwar Das
Sharma Arun
Sri-Jayantha Sri M.
International Business Machines - Corporation
Ryan & Mason & Lewis, LLP
Whitmore Stacy
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