Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-05-25
2001-11-06
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S205000, C365S201000, C714S718000, C714S726000, C714S733000, C714S742000
Reexamination Certificate
active
06314039
ABSTRACT:
TECHNICAL FIELD
The invention relates to computer memory systems generally. More particularly, the invention relates to characterization, testing and verification of sense amplifiers for use in computer memory systems.
BACKGROUND ART
One of the key components affecting the speed of a memory system is the sense amplifier, which is a differential amplifier or comparator that reads output lines from a memory array. One of the key characteristics affecting the speed of a memory is the offset voltage of its sense amplifier. A large offset voltage limits the speed at which a memory system can operate because memory array output lines must slew to a sufficient extent to overcome the offset voltage. To design a fast memory system, a designer must be able to predict sense amplifier characteristics, such as offset voltage. Unfortunately, known techniques for characterizing the offset voltage of the sense amplifier are approximate and unsatisfactory. Known techniques include calculations based on the electrical characteristics of the electronic components of the sense amplifier or rough “rules of thumb.”
SUMMARY OF INVENTION
In one respect, the invention is a circuit for characterizing a sense amplifier. The circuit comprises a sense amplifier having one or more inputs and an output, a BIT line connected to one of the one or more inputs of the sense amplifier, a register connected to the output of the sense amplifier; and control logic connected to the BIT line. Optionally, the register is further connected to the control logic, and the register is a scan register connectable to a tester. Preferably, the sense amplifier is a differential sense amplifier, and the circuit further comprises a complement BIT line connected to one of the one or more inputs of the sense amplifier.
In another respect, the invention is a system for characterizing a sense amplifier. The system comprises a means for amplifying one or more inputs to produce an output, a means, connected to one of the one or more inputs of the means for amplifying, for simulating an output of a memory array, a means for latching the output of the amplifying means; and a means for controlling the means for simulating. Optionally, the means for latching is further connected to the means for controlling, and the means for latching is a scan register connectable to a tester. Preferably, the system further comprises a means for simulating a complement output of a memory array. Preferably, the means for amplifying is a means for differentially amplifying two signals—the simulated output and the simulated complement output.
In yet another respect, the invention is a method for characterizing a sense amplifier. The method produces one or more signals like an output of a memory cell, operates one or more sense amplifier to produce one or more output states on the basis of the one or more signals, and records the one or more output states. Optionally, the method also records data related to the one or more signals. In one mode of operation, the method sets a voltage of the one or more signals like an output of a memory cell to be a static value during the operating step. In another mode of operation, the method sets a voltage of the one or more signals like an output of a memory cell to be alternating values during the operating step. The method further determines, on the basis of the one or more output states, whether the sense amplifier is acceptable, and if acceptable, the sense amplifier is utilized in a memory system.
In comparison to the prior art, certain embodiments of the invention are capable of achieving certain advantages, including the following:
(1) Accurate and extensive characterization of sense amplifiers, including their offset voltages, is possible.
(2) Alternate topologies, circuits and designs of sense amplifiers can be characterized.
(3) Aging and future drift of both the fabrication process making the sense amplifiers and the semiconductor devices containing the sense amplifiers can be simulated and tracked.
Those skilled in the art will appreciate these and other advantages and benefits of various embodiments of the invention upon reading the following detailed description of a preferred embodiment with reference to the below-listed drawings.
REFERENCES:
patent: 5434821 (1995-07-01), Watanabe et al.
patent: 5592425 (1997-01-01), Neduva
patent: 5835436 (1998-11-01), Ooishi
patent: 6006347 (1999-12-01), Churchill et al.
patent: 6175532 (2001-01-01), Ooishi
patent: 403078186A (1991-04-01), None
patent: 405081899A (1993-04-01), None
patent: 09120698A (1997-05-01), None
Hill J. Michael
Lachman Jonathan E.
McFarland Robert
Hewlett--Packard Company
Nguyen Viet Q.
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