Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-02-29
2004-10-26
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C257S775000
Reexamination Certificate
active
06809420
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit fabrication, and, more specifically, the present invention relates to metrology in the field of photolithography. In particular, the present invention relates to a methodology that uses multiple overlay targets that characterizes wafer-induced shift and tool-induced shift.
2. Description of Related Art
Metrology errors have traditionally consumed a small portion of the overall overlay budget. Registration is a measure of overlay error. Since design rules in advanced lithography processes require tighter overlay performance, these overlay errors become more significant as feature dimensions shrink. In a 0.18 micrometer (micron) process, the overlay requirement is less than 70 nm. Assuming a 10% overlay budget for metrology error, the overlay requirement translates to less than 7 nm of overall measurement uncertainty. The overall measurement uncertainty includes the inherent uncertainty and the tool induced shift (TIS) of the metrology tool, the variability of the overlay target, and the error that results from the bias between post develop condition (DC) of the mask and the after etch condition (FC) measurements.
FIG. 1
a
illustrates a prior art method of minimizing overlay measurement error. In
FIG. 1
a,
a semiconductor structure
10
comprises a substrate
12
, and a recess created in a layer
14
such as an interlevel dielectric layer (ILD). Upon ILD layer
14
and substrate
12
, an overcoating layer
16
such as a metallization film is formed. Upon overcoating layer
16
is patterned a mask
18
that is calculated to be substantially centered over the recess in ILD layer
14
. Measurement of how well centered mask
18
is over the recess in ILD layer
14
comprises the difference between A
1
and B
1
. If A
1
−B
1
is acceptable, an etch is conducted that creates a feature
20
as illustrated in
FIG. 1
b.
Subsequently, the measurement of how well-centered mask
18
was in the recess in ILD layer
14
can be done by calculating the difference between A
2
and B
2
.
In a typical lithography process, an exposure tool will lay down mask
18
as the current layer pattern, that attempts to be aligned to substrate
12
with the pattern of the previous layer
14
. The corresponding overlay structures are usually embedded under a thin film layer such as overcoating layer
16
to be patterned. After etching the pattern formed by mask
18
into overcoating layer
16
and stripping mask
18
, these structures are usually exposed and are easy for overlay tools to image.
Measurement of error can then be carried out. However, this measurement would be after-the-fact of the etch. Consequently, a poor overlay on a wafer could therefore not be corrected after etch (FC). Often measurement in a post develop condition (DC) is more applicable in a device manufacturing environment. Any overlay error that results from an unacceptable alignment could be corrected by stripping away the resist and by laying down a new pattern with the proper corrections. But where a poor quality placement of resist
18
occurs within the recess created in ILD layer
14
, it is too late to correct the error for the existing wafer because it is after etch (FC). In other words, where A
2
−B
2
is significantly larger than zero, the wafer must be discarded.
FIG. 2
a
illustrates the structure of
FIG. 1
a
in plan view.
FIG. 2
a
illustrates that A
1
is a measure between an edge of mask
18
and a feature near or at the outer box perimeter
22
. Similarly, B
1
is a measure between another edge of mask
18
and a feature near or at outer box perimeter
22
.
FIG. 2
b
illustrates the structure of
FIG. 1
b
in plan view.
FIG. 2
b
illustrates that A
2
is a measure between an edge of feature
20
and the outer box perimeter
22
. Similarly, B
2
is a measure between another edge of feature
20
and outer box perimeter
22
. As set forth herein, although the process of getting A
2
−B
2
to be equal to zero can be achieved by several approximations and corrections, the cost of arriving at this process may be several wasted substrates due to the fact that the etch required to achieve the structure depicted in
FIGS. 1
b
and
2
b
has resulted in an irreversible step. Where A
2
−B
2
is unacceptable, wafer yield is lowered.
To achieve the most accurate DC overlay measurement, such as is illustrated in
FIGS. 1
a
and
1
b,
overcoating layer
16
should be removed to expose the associated targets prior to laying down the resist pattern. However, this would require an extra etch operation which is unfavorable in terms of cost and time.
Measurements in DC are usually done while the overlay targets are still embedded. In certain cases, the thin film material is opaque and the overlay tool will image onto the topologies created by the profile of overcoating layer
16
on the top surface. For transparent films, images are formed through overcoating layer
16
, although the index of refraction of such transparent materials may render a measurement accuracy that is no better than estimation required with opaque overcoating layers
16
. In either case, the major source of measurement uncertainty comes from film material of overcoating layer
16
. Variations of film thickness, surface profile or optical properties result in a change in imaging condition of the overlay targets.
What is needed is a method that overcomes the problems in the prior art.
REFERENCES:
patent: 4323420 (1982-04-01), Masnari et al.
patent: 5539845 (1996-07-01), van der Tol
patent: 5834323 (1998-11-01), Ghafghaichi et al.
patent: 6004706 (1999-12-01), Ausschnitt et al.
patent: 6048588 (2000-04-01), Engelsberg
patent: 6188138 (2001-02-01), Bodo et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Picardat Kevin M.
LandOfFree
Characterization of induced shift on an overlay target using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Characterization of induced shift on an overlay target using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Characterization of induced shift on an overlay target using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3259910