Characteristic-evaluating storage capacitors

Details Characteristic-evaluating storage capacitors Characteristic-evaluating storage capacitors

1999-12-21

2001-10-09

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S068000, C438S014000

Reexamination Certificate

active

06300647

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device for characteristic evaluation and a method of a more particularly, to a semiconductor device used for evaluating the electrical characteristic of a capacitor or capacitors, and a method of evaluating the same using the device. The capacitor or capacitors have the same configuration as that of an objective capacitor or capacitors to be evaluated, such as storage capacitors incorporated into memory cells of semiconductor memory devices or other devices.
2. Description of the Prior Art
In recent years, the miniaturization and integration of semiconductor memory devices has been increasingly progressing and accordingly, there has been the increasing need to decrease the memory cell area per bit. In particular, with dynamic random-access memories (DRAMs), even if the memory cell area per bit is decreased, the storage capacitor of the memory cell must have a specific desired capacitance. To meet this need, various improved methods for forming the storage capacitor have ever been developed and disclosed. For example, the use of a high-dielectric-constant firm for the capacitor dielectric and the use of the hemispherical grain (HSG) silicon for capacitor electrodes have been disclosed.
On the other hand, in the semiconductor device fabrication field, the processes have been becoming advanced and complicated according to the miniaturization trend of DRAMs. Thus, the techniques aiming at the inspection and monitoring of the device quality during the fabrication process sequence have been becoming more important.
A typical example is the visual inspection of semiconductor wafers. If some contamination is generated in a process step of the fabrication process sequence, the semiconductor devices become faulty or defective at this process step. Therefore, the devices will be useless even if the wafers are subjected to the subsequent processes as desired, which results in decrease in their fabrication yield and increase in their fabrication cost. Consequently, it is important to find or detect the contamination in as early stages as possible.
With respect to the storage capacitors of DRAMs, similarly, it has been becoming important to measure the electrical characteristic of the storage capacitors for inspection during their fabrication process sequence. The most reliable method of measuring the capacitor characteristic such as the capacitance and the leakage current is to actually apply a specific voltage to the capacitor to be inspected and to measure its electrical characteristic in the operating state. However, this is very difficult to be performed, because the storage capacitors are incorporated into the memory cell. To solve this problem, conventionally, the following method has been used.
Specifically, “evaluating capacitors”, which are equivalent in configuration to the storage capacitors of the memory cell, are additionally formed on the same wafer as that of the DRAMs. Then, the electrical characteristic of the evaluating capacitors is measured, instead of the storage capacitors in the DRAM, memory cells. An example of the prior-art evaluating capacitors is shown in FIG.
1
.
FIG. 1
shows the configuration of a prior-art evaluating semiconductor device equipped with evaluating capacitors.
As seen from
FIG. 1
, the prior-art evaluating semiconductor device is equipped with a p-type single-crystal silicon (Si) substrate
101
, on which evaluating capacitors
120
are formed. An n-type diffusion region
102
is formed on the surface area of the substrate
101
. The diffusion region
102
is electrically isolated from other elements (not shown) by an isolation dielectric
103
.
A first interlayer dielectric layer
104
is formed on the substrate
101
to cover the diffusion region
102
and the isolation dielectric
103
. The layer
104
has contact holes
105
vertically penetrating through the same, exposing the surface of the diffusion region
102
. On the layer
104
, lower electrodes
106
, which are made of n-type polysilicon, are formed to be electrically connected to the underlying diffusion region
102
through the contact holes
105
.
A common capacitor dielectric
107
, which is made of silicon nitride (SiN
x
), is formed on the first interlayer dielectric layer
104
to cover the lower electrodes
106
. On the dielectric
107
, a common upper electrode
103
made of n-type polysilicon is formed to entirely overlap with the dielectric
107
. The upper electrode
108
is located to be opposed to the lower electrodes
106
. The lower electrodes
106
, the common upper electrode
108
, and the common capacitor dielectric
107
constitute the evaluating capacitors
120
.
A second interlayer dielectric layer
109
, which is made of silicon dioxide (SiO
2
), is formed on the first interlayer dielectric layer
104
to cover entirely the upper electrode
108
and the capacitor dielectric
107
on the layer
109
, upper wiring lines
110
a
and
110
b
are formed to be apart from each other. The wiring line
110
a
is electrically connected to the underlying upper electrode
108
by way of a contact hole
112
a
penetrating through the layer
109
. The wiring line
110
b
is electrically connected to the underlying diffusion region
102
of the substrate
101
by way of a contact hole
112
b
penetrating through the layers
109
and
104
.
With the prior-art evaluating semiconductor device shown in
FIG. 1
, the lower electrodes
106
are electrically connected to the wiring line
110
b
through the diffusion region
102
, and the common upper electrode
108
is electrically connected to the wiring line
110
a
. Therefore, to measure the characteristic of the evaluating capacitors
120
, a suitable measuring apparatus such as a capacitance meter is electrically connected to the electrodes
106
and
108
by way of the wiring lines
110
a
and
110
b
. The characteristic thus measured corresponds to that of the storage capacitors (not shown) in the DRAM memory calls formed on the same substrate
101
and therefore, the characteristic of the storage capacitors can be found.
However, the prior-art evaluating semiconductor device of
FIG. 1
has the following problems.
As seen from
FIG. 1
, a measuring apparatus is electrically connected to the upper wiring lines
110
a
and
110
b
, because it is unable to be directly connected to the lower electrodes
106
and the upper electrode
108
. Therefore, there is a problem that the characteristic measurement of the evaluating capacitors
120
needs to be performed after the completion of the formation steps of the wiring lines
110
a
and
110
b
on the second interlayer dielectric layer
109
. In other words, a problem that the characteristic of the capacitors
120
cannot be measured immediately after the completion of their formation steps will occur.
Moreover, if some fault or defect occurs in the characteristic of the capacitors
120
(i.e., the storage capacitors of the DRAM calls on the substrate
101
), the fault or defect will not be found until the characteristic measurement of the capacitors
120
is completed. In other words, time delay or lag cannot be avoided in coping with the generation of the fault or defect. As a result, the faulty DRAM cells are subjected to subsequent fabrication processes during the time lag. This means that there arises another problem that the fabrication yield decreases and the fabrication cost increases.
The Japanese Non-Examined Patent Publication No. 5-102264 published in April 1993 discloses a method of measuring the capacitance of DRAM cells.
In this prior-art method of 5-102264, an evaluating capacitor having the same configuration as that of a DRAM cell capacitor is formed within a testing chip. The evaluating capacitor is formed by a storage node (i.e. a lower electrode), a cell plate (i.e., an upper electrode), and a capacitor dielectric intervening between the storage node and the cell plate. The storage node is electrically connected to a device formation region (i.e., an active

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