Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2001-11-09
2003-04-29
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C714S700000
Reexamination Certificate
active
06557110
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a parallel redundancy encoder, that can be used for transmitting parallel data in information and communication processing systems, of a simple configuration requiring no clock speed conversion, and to a channel-to-channel skew compensation apparatus for the data being transmitted in a plurality of channels.
2. Description of the Related Art
The present invention is based on Patent Applications Nos. Hei 10-032618, Hei 10-059542 and Hei 10-077783 filed in Japan, contents of which incorporated herein by reference.
Processing speeds of data processing devices such as central processor unit (CPU) in information and communication systems have shown yearly increase in recent years, brought about by improvements in operating speed of large scale integration (LSI) devices. Along with this trend, there has been an increasing demand for data transfer speeds between data processing devices. Also, to improve processing capability of such systems, progress has been made in the technology for operating a plurality of devices in parallel, and there has been increasing demand for improved performance of data transmission over a long distance.
Optical data transmission is capable of transmitting data at high speeds over long distances, and expectations are high for its use within a system for the purpose of information processing and data communication. Within such a system, data are processed as 8-bit or 16-bit parallel data, and therefore, an optical data transfer system must also be capable of providing parallel data transfer. Data transfer based on optical devices is often carried out by encoding the data to obtain stability in d.c. signal level of incoming data and to enable detection and correction of data errors.
Data transmission duration in parallel data transmission systems described above can vary from channel to channel, because of differences in the performance characteristics of each channel and operating characteristics of communication circuitries, resulting in a scatter in data arrival times of data transmitted through different channels. For this reason, differences in arrival times are generated in the receiver-side of such parallel data transmission systems. The differences in data arrival times in different transmission channels are referred to as channel-to-channel skew.
When the speed of data transmission is slow or the distance of transmission is short, channel-to-channel skew is negligibly small compared with a unit clock time of the parallel interconnection system, such that it does not present a serious problem. However, as the speed of data transmission increases as the unit clock time of the parallel interconnection system becomes shorter in high speed transmission systems, data can no longer be received normally at the receiver terminal due to the channel-to-channel skew effects. Also, because the scatter in data arrival times caused by differences in the performance characteristics of the channels are proportional to the transmission distance, so the longer the distance of parallel data transmission the larger the channel-to-channel skew effects, and normal data communication becomes difficult.
For this reason, to increase the speed and distance of transmission of parallel interconnection systems, it becomes important to compensate for the channel-to-channel skew. In particular, increased transmission speed and distance in parallel interconnection systems can be more readily attained by optical methods rather than electrical methods, and compensation for channel-to-channel skew becomes critical. Therefore, encoding is often used in parallel interconnection to enable such compensation for channel-to-channel skew effects.
Here, one of the encoding methods known to enable skew compensation is to insert m′ bits of redundant data for each m bits of transmission data train in each channel, which called frame bits. In this encoding method, m-bits of transmission data and m′ bits of frame bits are combined to constitute a frame of m+m′ bits.
FIG. 20
illustrates an example of bit arrangement in such a frame.
An apparatus known widely for multiplexing data produced by parallel redundancy encoding is shown in FIG.
21
. Encoder
75
performs parallel/serial conversion of m-bit parallel data and m′-bit redundant data output from a redundant data generator
76
to a serial data train in a p-s conversion section
77
at m+m′:1 clock rate. One apparatus of parallel redundancy encoder
70
is comprised by arranging several encoders
75
in parallel.
In contrast,
FIG. 22
shows a functional block diagram of a parallel redundancy encoder that does not multiplex data for transmission. Encoder
75
inserts m′ bit of redundant data output from redundant data generator
79
for each m bits of data train input into a frame bit insertion section
78
at a bit speed of f
0
, and encodes the combined data by sending at a bit speed of (m+m′)/(m)×f
0
. One parallel redundancy encoder
70
is comprised by arranging several encoders
75
in parallel.
Other well known types of encoding method include “mB1A coding” which adds one auxiliary bit for each m bits of data. Variations of mB1A coding include a case of using the auxiliary bit as the parity bit, known as “mB1P coding”, and a case of using a coding bit for the preceding bit, known as “mB1C coding”. Also, in addition to those method that rely on inserting a special frame bit in frames in each channel, there are encoding methods that do not use frame bits, represented typically by “8B10B coding”.
Next,
FIG. 23
shows an example of the conventional channel-to-channel skew compensation apparatus received in the receiver channels that detects and compensate for the skewing amount in data generated by such parallel redundancy encoder described above. In the channel-to-channel skew compensator, shown in
FIG. 23
, pre-selected one channel among the parallel interconnections is designated as the reference group train, i.e., the master channel. Master channel frame sync circuit
82
enters master channel input data into the master channel and outputs master channel frame signals (sync signals) to indicate the input data positions along the time axis.
In all channels other than in the master channel, each frame sync circuit
83
enters own input data into respective channels, and generates frame signals to indicate the input data positions along respective time axes. In all channels other than the master channel, own comparison circuit
84
is provided. Each comparison circuit
84
compares frame signals in own channel with master channel frame signals. In other words, comparison circuit
84
determines how far ahead or behind its own frame signal is compared with the corresponding master frame signal, and outputs advance/delay information as a skew signal.
Input data into the master channel are delayed by the master channel data delaying circuit
85
for a pre-determined time duration. All input data other than the master channel data are delayed by their own data delaying circuit
86
. Each data delaying circuit
86
receives own skew signal, and adjusts the degree of skewing so as to match own frame position to the respective master frame position.
The location of master channel data delaying circuit
85
, whether it is in front or back of the master channel frame sync circuit
82
, does not affect the operating principle. Resulting from such series of adjustment steps, parallel data compensated for channel-to-channel skewing are generated.
However, in the conventional channel-to-channel skew compensation apparatus, should the degree of skewing is altered in the master channel, master signal timing is altered, i.e., reference positions of the master channel frame signals are altered. Therefore, in all the channels other than in the master channel, each comparison circuit
84
adjusts the degree of skewing produced by the respective data delaying circuits
86
. When the signal delay amount is
Ando Yasuhiro
Sakamoto Takeshi
Tanaka Nobuyuki
Finnegan Henderson Farabow Garrett & Dunner LLP
Heckler Thomas M.
Nippon Telegraph and Telephone Corporation
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