Channel router with buffer insertion

Details Channel router with buffer insertion Channel router with buffer insertion

2001-03-13

2003-01-07

Nguyen, Cuong Quang (Department: 2811)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06505336

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuits, and particularly to routing channels in integrated circuit chips. The invention is particularly useful in connection with fabrication of integrated circuit chips whose netlist is transmitted electronically by a customer to the IC foundry.
BACKGROUND OF THE INVENTION
Integrated circuits are typically composed of cells that are defined by netlists. The netlist defines the function of the cell, timing requirements and other factors associated with the fabrication of the integrated circuit chip. In most cases, channel size and pin function are defined by the netlist, taking into account technology restrictions of the fabrication process. Consequently, when developing the netlist, the IC designer selects the size of the channel, and any specialized timing considerations (including buffers) that may be required.
In some cases, the IC designer may not have full knowledge of the technology restrictions in connection with the fabrication of the integrated circuit chip. It is common, for example, for equipment manufacturers to design integrated circuit chips for use in their equipment and develop netlists of those chips. The netlists are then transmitted to the IC fabricator where modifications may be necessary to accommodate proprietary technology restrictions. This often means the chip designer and fabricator must coordinate efforts to modify the designer's netlists to accommodate the technology of the fabrication.
One area of chip fabrication requiring close coordination between the designer and the fabrication requirements lies in the area of channel definition and timing. Considerable time and effort are directed to channel definition. Moreover, even where the designer is fully knowledgeable of fabrication restrictions, complexities of channel design often render development of netlists that include channel design to be tedious. There is, accordingly, a need for a technique that automates the channel definition and timing to alter the original netlist for meeting fabrication requirements.
SUMMARY OF THE INVENTION
The present invention provides a technique to create channel routing of a channel and to insert buffers as may be necessary to accommodate timing requirements.
The present invention provides a process for routing channels in an integrated circuit layout. Input are definitions of (1) a grid having first and second orthogonal coordinate types, (2) netlists, (3) a channel dimension defined by coordinated of a first type, (4) timing requirements, and (5) technology restrictions for a plurality of cells of the integrated circuit. Grid positions are reserved for buffers. Pins of a cell are identified at different coordinates of the first type, such as at different y-coordinates, to be connected by the channel. A determination is made as to the necessity of a jog between vertical segments, and if so, a coordinate of the first type, such as a y-coordinate, is assigned to each such jog. A coordinate of the second type, such as an x-coordinate, is assigned to each channel segment extending across the y-coordinates. Coordinates of the first type, such as y-coordinates, are assigned to buffers to be connected to the channel.
In preferred embodiments, the necessity for jogs is determined by identifying whether pins of other netlists have the same coordinates, such as y-coordinates, as two pins on opposite sides of the channel of the cell under consideration. Coordinates are assigned to channel segments in accordance with technology restrictions, such as spacing, for the channel segments and jog.
In other preferred embodiments, coordinates are assigned to buffers for the channel by identifying if a segment extending along the y-direction crosses a coordinate of a reserved grid. If so, a buffer is coupled to the segment. If the segment does not cross the coordinate of the reserved buffer, the segment is extended to the coordinate of the reserved buffer, and a penalty is assigned to each extended segment. The buffers and segments are ordered to minimize the total penalty.
According to another aspect of the invention, a computer usable medium contains a computer readable program comprising code that causes a computer to define channel routing with buffer connections.


REFERENCES:
patent: 6453444 (2002-09-01), Shepard
A new toroidal mutli-domensional network Lee etal. IEEE Catalog No.: 97CH36074.

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