Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-07-21
1999-11-16
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714769, 714704, 360 53, G11C 2900
Patent
active
059876344
ABSTRACT:
A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.
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Behrens Richard T.
Bliss William G.
Foland, Jr. William R.
Abraham Esaw
Cady Albert De
Cirrus Logic Inc.
Sheerin Howard H.
Shifrin Dan A.
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