Channel processor using reduced complexity LDPC decoder

Details Channel processor using reduced complexity LDPC decoder Channel processor using reduced complexity LDPC decoder

2007-05-22

2007-05-22

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

Reexamination Certificate

active

10673181

ABSTRACT:
A low-density parity check device can process data using a special low-density parity check matrix having a size of n-rows by m-columns. By styling the matrix such that the matrix is composed of p equal-size sqaure sub-matrices, only the first row of the first sub-matrix need be generated and stored. By then further constraining each of the sub-matrices to form various sub-portions, with each sub-portion constructed such that any two columns within the sub-portion will have no common location containing a non-zero entry, processing advantages are gained.

REFERENCES:
Kurkoski et al., Joint message-passing decoding of LDPC codes and partial-response channels, Jun. 2002, IEEE Trans. on Info. Theory vol. 48, No. 6, p. 1410-1422.
Song et al., Applications of low-density parity-check codes to magnetic recording channels, May 2001, leee Journal on selected areas in COmm. vol. 19, No. 5, p. 918-923.
Futaki et al. Low-Density parity-check codes OFDM systems, 2001, IEEE, p. 82-86.
Mittelholzer et al. Reduced complexity decoding of low density parity check codes for generalized partial response channels, Mar. 2001, IEEE, Trans. on Magnetics, vol. 37., No. 2, p. 721-728.

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