Channel processing data without leading sync mark

Details Channel processing data without leading sync mark Channel processing data without leading sync mark

2006-11-07

2006-11-07

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error detection for synchronization control

C714S788000, C714S701000, C375S357000

Reexamination Certificate

active

07134068

ABSTRACT:
An apparatus and a method of aligning data bits serially received at a channel input. A number of data bits including a first data bit are stored in a buffer that has a first buffer bit and a buffer size greater than the number of data bits. The data bits in the buffer are shifted to improve alignment of the first data bit and the first buffer bit. The shifted data bits are tested for alignment. If the testing of the data bits indicates correct alignment, then the aligned data bits are transmitted from the buffer to a host for use. If the testing of the data bits indicates misalignment, then the data bits are passed to an error handling process.

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