Channel-less multithreaded DMA controller

Details Channel-less multithreaded DMA controller Channel-less multithreaded DMA controller

2007-10-16

2010-10-26

Nguyen, Tanh Q (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S005000, C710S019000, C710S023000, C710S024000, C710S033000, C710S034000, C710S035000, C710S036000, C710S039000, C710S040000, C710S042000, C710S052000, C710S305000, C710S308000, C710S310000, C712S228000, C712S229000, C718S108000

Reexamination Certificate

active

07822885

ABSTRACT:
A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

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