Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-15
2004-04-27
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S374000, C257S510000, C257S382000
Reexamination Certificate
active
06727558
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a semiconductor device, and a method of forming the semiconductor device.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. All other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also increases “short-channel” effects, almost by definition. Short-channel effects include, among other things, an increased drain-source leakage current when the transistor is supposed to be switched “off,” believed to be due to an enlarged depletion region relative to the shorter channel length. Short-channel effects also include threshold voltage (V
t
) rolloff (the rapid decrease in the threshold voltage V
t
for small changes in channel length &Lgr;), and large differences in the threshold voltage in the linear region V
tlin
and the threshold voltage in the saturation region V
tsat
(DIBL), so that V
t
is a strong function of the drain-source voltage V
ds
.
Short-channel effects may be reduced by using angled halo implants. Angled halo implants are implants of dopants that effectively “reinforce” the doping type of the substrate in the channel between the source/drain extension (SDE) regions (formerly known as lightly doped drain or LDD regions). For example, for an N-MOS transistor, the doping type of the substrate in the channel between the N
−
source/drain extension (SDE) regions is p-type. The angled halo implant may be boron (B) or boron difluoride (BF
2
) implanted into the substrate at an angle (with respect to a direction perpendicular to the surface of the substrate), and with a dose that may range from about 1.0×10
12
-1.0×10
14
ions/cm
2
at an implant energy ranging from about 5-15 keV for B and about 20-70 keV for BF
2
.
Similarly, for a P-MOS transistor, the doping type of the substrate in the channel between the P
−
source/drain extension (SDE) regions is n-type. The angled halo implant may be arsenic (As) implanted into the substrate at an angle (with respect to a direction perpendicular to the surface of the substrate), and with a dose that may range from about 1.0×10
12
-1.0×10
14
ions/cm
2
at an implant energy ranging from about 40-70 keV for As.
Moreover, reducing short-channel effects by using angled halo implants does not solve the problems associated with the increased contact and series resistances of active areas, such as N
+
(P
+
) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor. Reducing the channel length of a transistor also requires reducing the size and area of electrical contacts to the active areas. As the size and area of the electrical contacts to the active areas get smaller, the active area contact and series resistances increase. Increased active area contact and series resistances are undesirable for a number of reasons. For example, increased active area contact and series resistances may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor.
Typically, depositing titanium (Ti) or cobalt (Co) on the active area electrical contacts may decrease active area contact and series resistances. The Ti may then be silicided by annealing with a heat-treatment to form titanium silicide (TiSi
2
) at the active area electrical contacts (self-aligned silicidation or salicidation). The salicided TiSi
2
lowers active area contact resistance.
Nevertheless, effective salicidization may require the formation of deeper N
+
(P
+
) source/drain regions and/or deeper source/drain extension (SDE) regions. However, conventional techniques of forming deeper N
+
(P
+
) source/drain regions and/or deeper source/drain extension (SDE) regions typically increase undesirable short-channel effects such as increased drain-source leakage current.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided, the method including the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.
In another aspect of the present invention, a semiconductor device is provided, formed by a method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.
In yet another aspect of the present invention, a semiconductor device is provided including a gate dielectric above a substrate layer, and a gate conductor above the gate dielectric. The semiconductor device also includes at least one dielectric isolation structure in the substrate adjacent the gate dielectric.
REFERENCES:
patent: 6083796 (2000-07-01), Park et al.
patent: 6190981 (2001-02-01), Lin et al.
patent: 6383877 (2002-05-01), Ahn et al.
Aminpur Massud
Duane Michael P.
Luning Scott D.
Wu David D.
Duy Mai Anh
Fahmy Wael
Williams Morgan & Amerson
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