Channel interface signal tracing input/output controller apparat

Details Channel interface signal tracing input/output controller apparat Channel interface signal tracing input/output controller apparat

1998-01-16

2000-05-23

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

712227, 714 48, 714 57, 714 43, 714 56, 714 38, 714 34, 714 35, G06F 1328

Patent

active

060675888

ABSTRACT:
An input/output controller apparatus has a CPU arranged for directing an FPGA to generate a desired trace logic circuit and a channel controller to start communication with a host system. The channel controller while performing the communication with the host system delivers a channel sequence number via a buffer to the FPGA. In response, the FPGA saves the channel interface signal and the channel sequence number at given timing. When an error occurs during the communication, the CPU identifies the cause of the error by reviewing the channel interface signal and the channel sequence number saved in the FPGA. If the cause of the error fails to be identified, the FPGA is directed to generate another trace logic circuit suited for identifying the cause of the error. Accordingly, the size of a data storage used for tracing will be minimized and the overall area for installation of the apparatus will be minimized comparatively as well as the duration required for examining the communication between the host system and its peripherals will be reduced considerably. The apparatus may be linked to a plurality of host systems for equal advantages.

REFERENCES:
patent: 5070448 (1991-12-01), Crandall
patent: 5315500 (1994-05-01), Uchishiba et al.
patent: 5537607 (1996-07-01), Ploger, III
patent: 5751942 (1998-05-01), Christensen et al.
patent: 5752013 (1998-05-01), Christensen et al.
patent: 5758065 (1998-05-01), Reams et al.
patent: 5897653 (1999-04-01), Tashima

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