Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-03-30
2003-02-04
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C711S146000
Reexamination Certificate
active
06516442
ABSTRACT:
BACKGROUND
The system of
FIG. 1
is a prototypical prior art symmetric multiprocessor (SMP) system
100
. This traditional approach provides uniform access to memory
130
over a shared system bus
110
. Each processor
120
has an associated cache and cache controller. The caches are individually managed according to a common cache coherency protocol to insure that all software is well behaved. The caches continually monitor (snoop) the shared system bus
110
, watching for cache updates and other system transactions. Transactions are often decomposed into different component stages, controlled by different system bus signals, such that different stages of multiple transactions may be overlapped in time to permit greater throughput. Nevertheless, for each stage, subsequent transactions make sequential use of the shared bus. The serial availability of the bus insures that transactions are performed in a well-defined order. Without strong transaction ordering, cache coherency protocols fail and system and application software will not be well behaved.
A first problem with the above-described traditional SMP system is that the serial availability of the bus limits the scalability of the SMP system. As more processors are added, eventually system performance is limited by the saturation of the shared system bus.
What is needed is an SMP system architecture that provides greater scal ability by permitting concurrent use of multiple buses, while still providing a system serialization point to maintain strong transaction ordering and cache coherency. What is also needed is an SMP architecture that further provides increased transaction throughputs.
SUMMARY
A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems. Each end of a channel is connected to a Channel Interface Block (CIB). The CIB presents a logical interface to the Channel, providing a communication path to and from a CIB in another IC. CIB logic presents a similar interface between the CIB and the core-logic and between the CIB and the Channel transceivers. A channel transport protocol is is implemented in the CIB to reliably transfer data from one chip to another in the face of errors and limited buffering.
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Amdahl Carl G.
Biard Brian R.
Cohen Earl T.
Fu Daniel
Wang Yuanlong
Conexant Systems Inc.
De'cady Albert
Hale Kelly H.
Harris Cynthia
Kind Keith
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