Channel hot-carrier page write for NAND applications

Static information storage and retrieval – Floating gate – Particular biasing

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36518518, G11C 1134

Patent

active

058054995

ABSTRACT:
There is provided a novel method for performing low current channel hot-carrier programming in a NAND memory architecture. A first positive pulse voltage having a ramp-rate characteristic on its leading edge is applied to the drain of the select gate drain devices in the selected columns of bit lines during the programming operation. Simultaneously, a second positive pulse voltage is applied to the control gate of the select gate drain device and to the word lines of unselected memory cells so as to overlap the first positive pulse voltage. Further, a ramp voltage is applied to the word line of selected memory cells so as to permit fast programming thereof.

REFERENCES:
patent: 4611309 (1986-09-01), Chuang et al.
patent: 5068827 (1991-11-01), Yamada et al.
patent: 5544117 (1996-08-01), Nakayama et al.

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