Channel formation after source and drain regions are formed

Details Channel formation after source and drain regions are formed Channel formation after source and drain regions are formed

1999-05-25

2001-02-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S302000

Reexamination Certificate

active

06194293

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to fabricating semiconductor devices, and more particularly to ion implantation into the channel region.
BACKGROUND
Current processing methods for transistors, e.g., field effect transistors (FETs), metal oxide semiconductor devices (MOS), and complimentary MOS devices (CMOS), uses ion implantation in the channel region to control the threshold voltage of the device. The channel region becomes conductive when an appropriate gate to source voltage difference is applied to cause a conductive channel to form between the source and the drain. By controlling the channel dopant concentration, the threshold voltage may be controlled to achieve high performance transistors.
Conventionally, a blanket doping of the substrate with the intended channel implant is performed prior to gate formation. The gate oxide and gate are then formed followed by the source/drain regions. The implants are then activated with an annealing step. During the annealing step, transient enhanced diffusion occurs, causing the channel dopants (and the source/drain implants) to be redistributed in an uncontrolled fashion. Consequently, the channel dopant concentration is difficult to control using conventional methods.
Thus, there is a need for a method of forming well localized channel regions that is not redistributed by subsequent processing steps.
SUMMARY
In accordance with the present invention, a channel region is formed in a substrate after the source and drain regions are formed. By implanting ions into the channel region with a tilt angle, the location and concentration of the channel dopant is precisely controlled. A rapid thermal annealing step is then performed to activate the channel dopant. Because the source and drain regions are already formed, a relatively low temperature, e.g., 990 to 1010 degrees Celsius, and short, e.g., 1 to 5 seconds, rapid thermal annealing step may be performed to activate the channel region. Thus, the dopant concentration in the channel region is well localized and is not redistributed by subsequent processing. Because the implant is performed through the sidewall spacer, the energy is high enough that the channel is formed deep under the LDD extension regions, which advantageously prevents punchthrough.


REFERENCES:
patent: 5851886 (1998-12-01), Peng
patent: 5970353 (1999-10-01), Sultan
patent: 6020244 (2000-02-01), Thompson et al.
patent: 6030875 (2000-02-01), May et al.

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