Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-03-28
2002-04-16
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185230, C365S185270
Reexamination Certificate
active
06373749
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-102978, filed Apr. 9, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a nonvolatile semiconductor memory device, such as a flash EEPROM.
It is well known that a flash memory uses stacked-gate transistors as memory cells. A NOR flash EEPROM generally uses channel hot electrons in a write operation and FN tunnel current in an erase operation. There have been various methods of erasing data. For example, in an ETOX (EPROM Tunnel Oxide), a type of Intel's flash memory, an electric field is applied between the floating gate and the source by grounding the gate of a cell and applying a high voltage (about 10 V) to its source, thereby causing FN tunnel current to flow. Moreover, in the negative gate-source erasing method proposed by AMD Corp., a negative voltage (about −10 V) is applied to the gate of a cell in an erase operation and a positive voltage (about 5 V) is applied to its source, thereby causing FN tunnel current to flow between the floating gate and the source.
As the cell size is scaled down, a high voltage applied to the source of a cell in an erase operation becomes a problem. Use of a double diffused structure for the source region can be considered to improve the junction breakdown voltage so that the junction may withstand a high voltage. Specifically, an N
+
(As) region as the source region is covered with an N
−
(P) region, thereby improving the breakdown voltage. The double diffused structure, however, is a factor that prevents the channel length from being scaled down. Specifically, when an N
−
region is formed to secure a sufficient breakdown voltage, the overlap length Y
j
of the diffused layer and the gate increases. The overlap length Y
j
is estimated at about 0.2 &mgr;m. When the devices are miniaturized further and particularly the coming generation of 0.25 &mgr;m or less in size is taken into account, the channel length L including the Y
j
part is:
L=Leff+0.2 &mgr;m>>0.25 &mgr;m
where Leff is the effective channel length.
Thus, the channel length has a significantly adverse effect on the reduction of the cell size.
To overcome this problem, a channel erasing method has been developed. In this method, a high voltage is applied between the substrate (=source) and the word line, thereby causing tunnel current to flow between the floating gate and the substrate. Since the substrate and source have the same potential (the source may be in the floating state), there is no need to take into account the junction breakdown voltage of the source, eliminating the necessity of a double diffused structure.
However, since the method has a large capacity between the floating gate and the substrate, a high voltage must be applied between the gate of the cell and the substrate in an erase operation, as compared with the source erasing method. Therefore, the breakdown voltages of the transistors constituting a decode circuit for supplying a specific voltage to the gate of a cell (word line) or a decode circuit for supplying a specific voltage to the substrate become a problem. To avoid this, the voltages at various sections have been considered to prevent the breakdown voltages of those transistors from becoming a problem.
FIGS. 6A
,
6
B, and
6
C show the relationship between the bias voltages supplied to various sections of a memory cell. As shown in
FIGS. 6A and 6B
, to suppress the breakdown voltage to a lower level, it is desirable that a negative voltage (Vg=−8 V) should be applied to the control gate of a cell in an erase operation and a positive high voltage (Vsub=10 V) should be applied to the substrate. In the case of channel erasing, a memory cell MC is formed in a p-type well isolated from a p-type substrate by an n-type well. A substrate voltage Vsub in the cell is supplied to the p-type well and n-type well.
With the method, a decode circuit can be composed of transistors with a breakdown voltage of 10 V. In contrast, an attempt to cause only the control gate or substrate to have resistance to voltage requires transistors with a breakdown voltage of about 20 V. Thus, as the breakdown voltage of the transistor increases, tox. (the film thickness of the oxide film), L (the channel length), and the like must be twice those of a transistor with a breakdown voltage of 10 V. This makes the decode circuit larger. Consequently, the area the decode circuit occupies on the chip is enormous.
FIGS. 7
to
9
show examples of circuits for applying a channel erase bias voltage to various section of a cell.
FIG. 7
shows an example of a row decode circuit (word line driver). In the row decode circuit, a logic circuit
71
a
decodes address signals in a voltage 0-Vdd system and an Erase signal. The decode output signal from the logic circuit
71
a
is converted by a level shifter
71
b
into signals in a voltage V
SW
, V
BB
system. The voltage V
SW
is the high level of the word line and the voltage V
BB
is the low level of the word line. The output signal of the level shifter
71
b
is supplied as a voltage V
WL
to the word line via an inverter circuit
71
c
acting as a driving circuit.
FIG. 9
shows the voltage V
WL
on a word line. In this way, the voltage V
WL
on the word line is set according to the reading, programming, and erasing of the data. The absolute value of each of the voltage V
SW
, V
BB
is set at 10 V or less, which satisfies the breakdown condition of the transistors in the decode circuit.
FIG. 8
shows an example of the configuration of the level shifter shown in FIG.
7
.
FIG. 10
shows an example of a decode circuit for supplying a potential to a substrate (p-type well) in which a cell array is formed. In the decode circuit, a logic circuit
100
a
decodes a block address signal and an Erase signal. The decode output signal of the logic circuit
100
a
is supplied to a level shifter
100
b
, which converts it into a voltage V
H
and a signal of the ground level. The voltage V
H
is, for example, 10 V. The output signal of the level shifter
100
b
is supplied to a p-type well via an inverter circuit
100
c
acting as a driving circuit.
A problem encountered in realizing the negative gate channel erasing method will be explained.
FIG. 11
is a sectional view of an n-channel transistor (NMOS), a p-channel transistor (PMOS) and a memory cell (MC) in the decoder.
FIG. 12
shows an equivalent circuit of FIG.
11
. There are parasitic capacitances C
1
to C
5
between the n-channel transistor, p-channel transistor, and memory cell.
FIG. 13
shows an equivalent circuit of the parasitic capacitances C
1
to C
5
. The parasitic capacitances C
1
to C
5
are as follows:
C
1
: a capacitance between the control gate of a memory cell and the substrate (p-type well)=a series capacitance of (a capacitance between the control gate and the floating gate) and (a capacitance between the floating gate and the substrate).
C
2
: a capacitance between a block substrate (n-type well or p-type well) and the substrate.
C
3
: a capacitance between the high level in the decoder (n-type well) and the substrate.
C
4
: a capacitance between the high level (V
SW
) and low level (V
BB
) in the decoder.
C
5
: a capacitance between the low level (V
BB
) in the decoder and the substrate.
After an erase operation has been completed, this type of nonvolatile semiconductor memory device has to be reset to the state that allows a read operation. Specifically, the voltage V
WL
on the word line must be changed from −8 V to 0 V and the voltage V
well
at the well must be changed from 10 V to 0 V. A problem encountered in resetting the voltage on the word line and the voltage at the well is the order in which the respective nodes are reset.
FIGS. 14 and 15
illustrate how each node is reset after the completion of the erasure, using extreme examples.
FIG. 14
shows
Atsumi Shigeru
Tanzawa Toru
Taura Tadayuki
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