Channel accelerated tunneling electron cell, with a select regio

Details Channel accelerated tunneling electron cell, with a select regio Channel accelerated tunneling electron cell, with a select regio

1995-03-28

1997-10-07

Saadat, Mahsid D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257319, 36518526, 36518533, H01L 2976, H01L 29788, H01L 29792, G11C 1134

Patent

active

056751613

ABSTRACT:
Improved non-volatile memory cells capable of being written and erased electrically, suitable for high density low voltage applications are disclosed. Writing the cells is by using the Channel Accelerated Carrier Tunneling (CACT) method for programming memories, (patent application Ser. No. 08/209,787 filed on Mar. 11, 1994) and the erase is by tunneling through a thin oxide region. Two structural embodiments are disclosed. First embodiment, Trenched-Channel Accelerated Tunneling Electron cell (Tr.sub.-- CATE), and a second embodiment Trench Wall-Channel Accelerated Tunneling Electron cell (Tw-CATE), both make use of separate regions of the channel for write and erase and hence provide high reliability of operation. The cells disclosed use a vertical step etch to form part of the channel to accelerate the carriers and also to act as a select gate without increasing the cell area. By separating the portion of the gate on the side wall from that over the surface, along a continuous channel between the source and drain, independently operating storage region and a select/accelerating region are formed along the same channel. This structure allows independent voltages to be applied to the storage gate and the accelerating gate. These CATE cells allow low supply current operation. Since all the operations are low current operations, efficient pumps can be used on chip to provide the required high voltages where needed.

REFERENCES:
patent: 5071782 (1991-12-01), Mori
patent: 5359218 (1994-10-01), Taneda
patent: 5455792 (1995-10-01), Yi
"Vertical EEPROM Cell"; IBM Technical Disclosure Bulletin, vol. 35, No. 4B, Sep. 1992, pp. 130-131.

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