Chained DMA devices for crossing common buses

Details Chained DMA devices for crossing common buses Chained DMA devices for crossing common buses

1990-10-01

1997-09-02

Elmore, Reba I.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

364DIG1, 711163, 395842, G06F 1336

Patent

active

056641427

ABSTRACT:
Chaining or cascading two or more DMA devices to perform DMA transfers across common buses. DMA devices are modified to act as a bus slave relative to another DMA bus master device so that information can be transferred from one bus to another across a third bus common to the DMA devices. The slave DMA can cause the master DMA to stop sending data to limit the bandwidth requirements of the common bus.

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Article titled "High-Speed Multi-Master Channel Interface", IBM Technical Disclosure Bulletin, vol. 30, No. 11, Apr. 1988, pp. 317-319.
Article titled "Direct Memory Access Controller (DMAC)", Microprocessor, Microcontroller and Peripheral Data, vol. 11, DL139, 1988.

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