Chained cache coherency states for sequential homogeneous...

Details Chained cache coherency states for sequential homogeneous... Chained cache coherency states for sequential homogeneous...

2008-05-06

2008-05-06

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S124000, C711S146000, C709S216000

Reexamination Certificate

active

07370155

ABSTRACT:
A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to track the chain of processor requests and subsequent access permission provided, prior to receipt of the data at the first processor starting the chain. The chained intermediate coherency state assigned identifies the processor operation and a directional identifier identifies the processor to which the cache line is to be forwarded. When the data is received at the cache of the first processor within the chain, the first processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chain is immediately stopped when a non-homogenous operation is snooped by the last-in-chain processor.

REFERENCES:
patent: 2002/0078310 (2002-06-01), Frank et al.
patent: 2004/0030842 (2004-02-01), Cypher
patent: 2004/0093467 (2004-05-01), Shen et al.

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