Chained cache coherency states for sequential...

Details Chained cache coherency states for sequential... Chained cache coherency states for sequential...

2005-10-06

2008-08-05

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S124000, C711S146000, C709S216000

Reexamination Certificate

active

07409504

ABSTRACT:
A method for sequentially coupling successive processor requests for a cache line before the data is received in the cache of a first coupled processor. Both homogenous and non-homogenous operations are chained to each other, and the coherency protocol includes several new intermediate coherency responses associated with the chained states. Chained coherency states are assigned to track the chain of processor requests and the grant of access permission prior to receipt of the data at the first processor. The chained coherency states also identify the address of the receiving processor. When data is received at the cache of the first processor within the chain, the processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chained coherency protocol frees up address bus bandwidth by reducing the number of retries.

REFERENCES:
patent: 2002/0078310 (2002-06-01), Frank et al.
patent: 2004/0030842 (2004-02-01), Cypher
patent: 2004/0093467 (2004-05-01), Shen et al.

Affiliated with

Also associated with

Rating

Chained cache coherency states for sequential... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chained cache coherency states for sequential..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chained cache coherency states for sequential... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4008402