Chain-type ferroelectric random access memory (FRAM) with...

Details Chain-type ferroelectric random access memory (FRAM) with... Chain-type ferroelectric random access memory (FRAM) with...

2002-08-27

2003-04-22

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S209000, C365S205000, C365S190000, C365S196000, C365S202000

Reexamination Certificate

active

06552922

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory used in integrated memory circuits and integrated memory circuits for use with logic devices and more specifically to a ferroelectric random access memory and a chain type ferroelectric random access memory having memory cells of conventional architecture operated at low boost voltages, also to DRAM, a ferroelectric random access memory and a chain type ferroelectric random access having memory cells of conventional architecture operated by a negative word line method or a boosted sense ground method at low boost voltages.
The ferroelectric material has a hysteresis character in the relationship between applied electric field and induced polarization, wherein if the voltage applied across the electrodes of a ferroelectric thin film is returned to zero, some magnitude of polarization remains. Namely, the polarization generated when a voltage was applied is maintained even after the applied voltage has been removed. Another characteristic feature of this material is that if a certain magnitude of inverse voltage is applied, the direction of polarization is accordingly inverted in the ferroelectric material.
With focus on the above characteristics of the ferroelectric material, a ferroelectric random access memory has been developed that has an array of memory cells where the polarization in a ferroelectric thin film is stored as logical information.
There are two representative structures for ferroelectric random access memory cells: a structure in which a ferroelectric thin film is used as an insulative thin film inserted between the two electrodes of a capacitor that holds information; and the other structure in which a ferroelectric thin film is used as the gate insulative film in a MOS transistor used for switching operation.
The former structure is obtained by replacing the capacitor in the DRAM cell with a ferroelectric capacitor. Dipole charge of either two directions of polarity is taken out from the ferroelectric capacitor through a MOS transistor that serves as a transfer gate. Since this operation is a destructive readout, the read data is written back after readout.
The following are the basic structure, characteristics and principles in write/read operations of the former type of ferroelectric random access memory cells.
As types of ferroelectric random access memory cells, there are a 1T1C-type cell of which equivalent circuit is shown in
FIG. 25A and a
2T2C-type cell comprising two 1T1C-type cells of which equivalent circuit is shown in FIG.
27
A.
In the 1T1C-type cell shown in
FIG. 25A
, a MOS transistor Q as a transfer gate and a ferroelectric capacitor C serving as memory are electrically connected in series. A word line WL is electrically connected to the gate of the MOS transistor Q, a bit line BL to an electrode (drain) of the MOS transistor Q, and a plate line PL to an electrode (plate) of the capacitor C.
FIG. 25B
is a hysteresis loop that explains how the 1T1C-type ferroelectric random access memory cell shown in
FIG. 25A
reads logical data “0” and “1”, indicating the relationship between a voltage (difference between the plate line voltage VPL and the bit line voltage VBL) applied to a ferroelectric thin film inserted between the electrodes of a ferroelectric capacitor and the magnitude of induced polarization P(C/m). The points “a” and “b” represent the magnitude of remnant polarization.
As hysteresis characteristics shown in
FIG. 25B
indicate, a cell can represent two different logical states by two residual polarization (Pr) points, “a” and “b”, which are the magnitudes of polarization observed when no voltage (V=0) is applied across the electrodes of the ferroelectric thin film in a ferroelectric capacitor.
Next, the principles of read/write operations in a 1T1C-type ferroelectric random access memory cell are explained with reference to the hysteresis loop shown in FIG.
25
B.
First, the bit line voltage VBL is equalized to the ground voltage at the precharge cycle, and then the equalization is released. After the transistor Q is turned on and the word line WL is selected, the plate line voltage VPL is elevated from the ground voltage to the supply voltage to extract the charge stored in the capacitor C to the bit line. The resulting change in the bit line voltage is compared with the reference voltage generated from a cell for reference use and amplified by a sense amplifier (not shown).
When data “0” is read, the polarity in the capacitor C is not inverted and the amount of electric charge read out to the bit line is small. As a result of comparative amplification by the sense amplifier, the bit line (on the side of storage node in the capacitor C) voltage becomes equal to the ground voltage. Thus the polarization of the capacitor C moves from point “a” to point “c” on the hysteresis curve.
On the other hand, when data “1” is read, the polarity in the capacitor C is inverted and the amount of charge read out to the bit line when the supply power voltage is applied as the above plate line voltage VPL is larger than that in the operation of reading “0”. As a result of comparative amplification by the sense amplifier, the bit line (on the side of storage node in the capacitor C) voltage becomes equal to the supply power voltage. Thus the polarization in the capacitor C moves from point “b” to point “c” and then point “a” on the hysteresis curve.
Next, the data latched in the sense amplifier is sent to a data line (not shown) and the plate line voltage VPL is reduced to the ground voltage. Then, the polarization state moves back to point “a” when reading data “0” and moves to point “d” when reading data “1”.
Later, when the transistor Q is turned off, the polarization state moves from point “d” to point “b” when reading “1” and then the rewrite operation to the capacitor C is completed.
The above was an explanation of read/rewrite operations. When new data is written, the voltage equal to the supply power voltage should be applied to the bit line if data “1” is written, and the voltage equal to the ground voltage to an input/output line (not shown) if data “0” is written, while the supply power voltage is applied to the plate line.
In the 2T2C-type cell shown in
FIG. 26A
, a first bit line BL is electrically connected to an electrode of the first transistor Q
1
in the first cell, and a second bit line /BL, paired with the first bit line BL, is electrically connected to an electrode of the second transistor Q
2
in the second cell. The gates of two transistors Q
1
and Q
2
have a common word line WL, and the plate electrodes of the two capacitors C
1
and C
2
have a common plate line PL. The above two bit line BL and /BL are electrically connected to a sense amplifier (not shown) for amplifying the bit line sense voltage and an equalizer circuit (not shown), for example.
Next, the principles of read/write operations in the 2T2C-type ferroelectric random access memory cell are explained.
FIGS. 26A
to
26
D indicate the applied voltage and the state of polarization in the ferroelectric capacitor during write operation.
FIGS. 27A
to
27
C indicate the applied voltage and the state of polarization in the ferroelectric capacitor during read operation.
FIG. 28
shows the voltage applied to the plate line during above data write and read operations. During write and read operations in the ferroelectric memory cell, the direction of polarization is controlled by changing the plate voltage PL in the selected memory cell as 0V→3V→0V, for example.
(A) In the case of writing data, the plate line voltage PL is set to 0V at first, and the voltages of the bit line pair BL and /BL are equalized to 0V. Now it is assumed that the two capacitors C
1
and C
2
have polarization of which directions are opposite to each other as shown in FIG.
26
A.
First, the equalization of the bit lines is released. Next, as shown in
FIG. 26B
, 4.5V, for example, is applied to the word line WL and the two transistors Q
1
and Q
2
are turned on. Then 3V, for example, is

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