Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2007-11-13
2007-11-13
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S189070, C365S190000
Reexamination Certificate
active
11382098
ABSTRACT:
A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
REFERENCES:
patent: 4494219 (1985-01-01), Tanaka et al.
patent: 4531202 (1985-07-01), Watanabe et al.
patent: 4831589 (1989-05-01), Brahmbhatt
patent: 5754466 (1998-05-01), Arase
patent: 5903492 (1999-05-01), Takashima
patent: 6094370 (2000-07-01), Takashima
patent: 6300654 (2001-10-01), Corvasce et al.
patent: 6483737 (2002-11-01), Takeuchi et al.
patent: 6735733 (2004-05-01), La Rosa
patent: 7002842 (2006-02-01), Tang et al.
patent: 7057927 (2006-06-01), Tang et al.
patent: 19724449 (1997-12-01), None
patent: 0293798 (1988-12-01), None
patent: 0631287 (1994-12-01), None
patent: 1-158691 (1989-06-01), None
patent: 9-120685 (1997-05-01), None
patent: 10-255483 (1998-09-01), None
patent: 11-177036 (1999-07-01), None
D. Takashima, et al., “Gain Cell Block Architecture for Gigabit-Scale Chain Ferroelectric RAM,” 1999 Symposium on VLSI Circuits, pp. 103-104.
D. Takashima et al., “High-Density Chain Ferroelectric Random-Access Memory (CFRAM),” Symposium on VLSI Circuits Digest of Technical Papers, 1997, pp. 83-84.
D. Takashima et al., “A Sub-40ns Random-Access Chain FRAM Architecture with a 7ns Cell-Plate-Line Drive,” ISSCC Digest of Technical Papers, Feb. 15, 1998, pp. 102-103, and 450.
JP Office Action, JP Appln. 11-155131, mailed Aug. 8, 2006.
Ogiwara Ryu
Oowaki Yukihito
Takashima Daisaburo
Takeuchi Yoshiaki
Tanaka Sumio
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Tran Andrew Q.
LandOfFree
Chain ferroelectric random access memory (CFRAM) having an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Chain ferroelectric random access memory (CFRAM) having an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chain ferroelectric random access memory (CFRAM) having an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3825116