Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-10-23
2004-09-28
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S100000, C710S316000
Reexamination Certificate
active
06799239
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to buses for interconnecting computer subsystems.
2. Background Art
Computer systems typically include one or more buses to permit communication between interconnected subsystems. One common type of subsystem interconnect is the parallel bus. Corresponding lines from each subsystem are connected together by cables or a backplane. Typically a bus master resolves contentions for access to the bus. Once a subsystem is granted access to the bus, the subsystem broadcasts information to all other subsystems in parallel. Parallel buses provide a rapid and efficient means for communicating information between subsystems. However, the entire bus may function incorrectly due to certain types of faults in a single subsystem. Further, bus contention and conflict may result in latency seen by a transmitting subsystem.
A second type of bus system interconnects each subsystem in a sequential or daisy chain fashion. Typically, such daisy chaining uses a high speed serial interconnect between logically adjacent subsystems. Information is transmitted from subsystem to subsystem along the daisy chain until it reaches the destination subsystem. Daisy chained buses typically experience long latencies as compared to parallel buses. Also, hot swapping or a fault in one subsystem may brake the chain rendering the bus inoperative.
What is needed is a subsystem interconnect that delivers information at high speed simultaneously to each subsystem. Further, the subsystem interconnect should be capable of surviving any fault within one or more subsystems.
SUMMARY OF THE INVENTION
The present invention receives data from each subsystem and simultaneously broadcasts the data to all subsystems. Thus, the present invention eliminates inter-subsystem latency. The present system is also tolerant of subsystem faults and hot swapping.
A computer system having a plurality of subsystems is provided. The computer system includes bus interface logic in each subsystem. The bus interface logic converts data from the subsystem into serial format for transmission and converts serial data received into a format usable by the subsystem. Each of a plurality of serial output paths carries serial data to one of the subsystems. Each of a plurality of serial input paths carries serial data from one of the subsystems. Communication interconnection logic receives data from bus interface logic through a corresponding serial input path. The received input data is buffered if the serial output paths are in use. Received data is simultaneously transmitted to each bus interface logic through all serial output paths.
In an embodiment of the present invention, bus interface logic includes a portion of the communication interconnection logic.
In another embodiment of the present invention, the communication interconnection logic includes a buffer associated with each serial input path for buffering received input data.
In yet another embodiment of the present invention, the communication interconnection logic monitors each serial input path and determines whether or not data on any path is faulty. Faulty data is not transmitted out to each bus interface logic.
In still another embodiment of the present invention, the communication interconnection logic determines the status of each bus interface logic by monitoring the serial input paths.
In a further embodiment of the present invention, each subsystem is implemented on a separate board within the computer system.
A method of interconnecting subsystems in a computer system is also provided. Serial data is transmitted from at least one subsystem to communication interconnection logic. The transmitted data is buffered in the communication interconnection logic if output serial paths to each subsystem are in use. The serial data is simultaneously transmitted from the communication interconnection logic to each subsystem when the output serial paths are not in use.
In an embodiment of the present invention, at least one subsystem supports a plurality of communication channels. Serial data is received by bus interface logic on the subsystem from at least one communication channel supported by the subsystem. The received serial data is buffered if an input serial path from the subsystem to the communication interconnection logic is in use. The received communication channel data is sent to the communication interconnection logic if the input serial path from the subsystem to the communication interconnection logic is not in use. Serial data is received on the output serial path from the communication interconnection logic to the subsystem. The received serial data is simultaneously transmitted on the output serial path to each communication channel of the subsystem.
An interconnection network interconnecting a plurality of computer components is also provided. The interconnection network includes a plurality of boards. Each board communicates with at least one computer component through a communication channel. Each board has bus interface logic for sending and receiving interconnection network commands. A data interconnect network establishes at least one data path between the boards. Each of a plurality of serial output paths carries serial commands to one of the boards. Each of a plurality of serial input paths carries serial commands from one of the boards. Communication interconnection logic receives serial commands from bus interface logic through a corresponding serial path. The received input commands are buffered if the serial output paths are in use. All received commands are transmitted to each bus interface logic through corresponding serial output paths. The communication interconnection logic controls the data interconnection network to establish at least one connection between the boards.
The above objects and other objects, features, and advantages of the present invention are readily apparent from the following detailed description of the best mode for carrying out the invention when taken in connection with the accompanying drawings.
REFERENCES:
patent: 2001/0014925 (2001-08-01), Kumata
Brooks & Kushman P.C.
Lefkowitz Sumati
Storage Technology Corporation
LandOfFree
Centrally distributed serial bus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Centrally distributed serial bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Centrally distributed serial bus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3245219