Central processing unit including address generation system...

Details Central processing unit including address generation system... Central processing unit including address generation system...

2005-04-05

2005-04-05

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Slip control, misaligning, boundary alignment

C711S219000, C711S220000, C712S204000, C712S205000

Reexamination Certificate

active

06877082

ABSTRACT:
A disclosed address generation system includes a decrementer and a multiplexer. The decrementer produces a decremented address signal by subtracting a first integer value from an incremented address signal. The multiplexer produces either the incremented address signal or the decremented address signal dependent upon a control signal. A described instruction fetch apparatus includes an instruction queuing and selection subsystem producing either an even portion or an odd portion of an instruction data block, specified by a first address signal, as a fetched instruction dependent upon one or more control signals generated based on determining bits of second and third address signals. A disclosed central processing unit (CPU) includes an instruction cache and a processor core, wherein the processor core includes an address generation subsystem generating the first, second, and third address signals, and the instruction queuing and selection subsystem. A method is described for fetching an instruction.

REFERENCES:
patent: 5941980 (1999-08-01), Shang et al.
patent: 6574724 (2003-06-01), Hoyle et al.

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