Central processing unit compatible with bank register CPU

Details Central processing unit compatible with bank register CPU Central processing unit compatible with bank register CPU

1996-07-16

2001-07-24

Verbrugge, Kevin (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C703S027000

Reexamination Certificate

active

06266756

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to central processing units and more particularly to a central processing unit having a register of an expanded size and having addressing capability compatible with an lower-class central processing unit in which a bank register is used, by simulating addressing of the lower-class central processing unit.
2. Description of the Prior Art
An addressing scheme in which data is referred to by using a register as a pointer is called indirect addressing. When indirect addressing using a register (hereinafter, referred to as register indirect addressing) is performed in a central processing unit (hereinafter, referred to as a CPU)
1
equipped with a 16-bit general-purpose register W
0
, addresses 0000h-FFFFh in a memory are accessible, that is, a memory area of 64 kbytes (=2
16
) is available. Any address (for example, the address “1234h”) has a 16-bit notation in this scheme. When such an address is stored in the above-mentioned 16-bit general purpose register W
0
, addressing using the general purpose register W
0
as a pointer is made possible.
One of the methods for expanding an accessible area in a memory is known as a bank addressing. In bank addressing, lower bits of address data are stored in the general purpose register W
0
, and higher bits of address data are stored in a data bank register DBR. According to this scheme, any address is represented using data in the data bank register DBR and data in the general purpose register W
0
(see Japanese Laid-Open Patent Applications No.64-91254, No.62-89294, No. 51-132047, No.1-92851 and No.3-204029).
A description will now be given of register indirect addressing using the bank addressing. It is assumed that an address having a size exceeding the size (16 bits) of the general purpose register W
0
is given. If we take an example of “123456h”, the lower portion which fits the 16-bit notation, that is, “3456h” is stored in the 16-bit general purpose register W
0
, and the higher 8-bit portion “12h” is stored in the data bank register DBR. A command may specify the general purpose register W
0
holding the lower 16-bit address portion while at the same causing the data bank register DBR to output the higher 8-bit data. Given that the data bank register DBR has a 8-bit capacity and the general purpose register Wo has a 16-bit capacity, a memory area representable by a 24-bit (8+16) notation is accessible. That is, a memory area as large 16 megabytes (=2
24
) is available.
When the register indirect addressing is performed in a CPU
2
equipped with a 32-bit general-purpose register W
1
, it is possible to access a memory area exceeding the 64-kilobyte limitation without using the data bank register DBR. That is, the aforementioned exemplary address “123456h” is stored as it is in the 32-bit general purpose register W
1
so that the bank register DBR is not necessary.
In case that the CPU
2
is an downward compatible model for the CPU
1
, that is, in case the CPU
2
is capable of executing programs written for the CPU
1
, but the CPU
1
is not necessarily capable of executing programs written for the CPU
2
, the CPU
2
is expected to execute programs written for the CPU
1
. Hence, the data bank register DBR is included in a programming model for the CPU
2
. Accordingly, it is necessary for the CPU
2
to be adapted for register indirect addressing using the data bank register DBR.
It is conceivable that both the indirectly addressing using a 16-bit register and the indirect addressing using a 32-bit register are provided in the CPU
2
. However, such an arrangement increases the number of indirect addressing schemes used, in proportion to the number of registers used (more specifically, a range of register IDs specified). An increase in the number of addressing schemes produces disadvantages such as an increase in a command code length and a decrease in the number of command types.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a central processing unit in which the aforementioned problem is eliminated.
Another and more specific object of the present invention is to provide a central processing unit having a register of an expanded size and having addressing capability compatible with an lower-class central processing unit in which a bank register is used, by simulating addressing of the lower-class central processing unit.
Assuming that the CPU
2
having a 32-bit register processes a program written for the higher-class CPU wherein 16-bit data is written in the 32-bit register, the higher 16 bits are meaningless. The entirety of the 32-bit data in the 32-bit register is not read. That is, even when the lower 16-bit data is rewritten, the 32-bit register is not used in register indirect addressing.
Rewriting of 16-bit data also occurs when the CPU
2
having a 32-bit register processes a program written for the lower-class CPU. In this case, the 32-bit register in which the 16-bit data is rewritten may be used in register indirect addressing. Indirect register addressing in such a case is a process of adding data in a data bank register (DBR) to the 16-bit data in the 32-bit register. The data in the data bank register may be referred to as a fixed value because once set this data is held fixed. In this adding process, the data in the data bank register is copied to the higher 16-bit area in the 32-bit register. The resultant 32-bit data in the 32-bit register may be delivered to a subsequent process.
The central processing unit of the present invention comprises a first register and a second register having a smaller bit size than the first register. Storing in the first register of data not as long as the bit length of the first register is performed such that 16-bit data, for example, is forwarded from the second register to the bit positions in the first register not filled (i.e. the higher 16 bit positions).
A description will now be given of how register indirect addressing is implemented when a program for the higher-class CPU is executed. When 32-bit data is written in the first register, the 32-bit data is output as an address. When 16-bit data is written in the first register, another 16-bit data is forwarded from the second register to the higher portion of the first register, resulting in 32-bit data obtained as a result of expanding the 16-bit data. Accordingly, a lower-class CPU program that causes 16-bit data to be stored in the first register may employ the same register indirect addressing scheme as used for the 32-bit data.
The process of supplying 16-bit data, for example, from the second register to the unfilled higher 16 bit positions of the first register may be executed using one command.
More specifically, when the data in the second register is modified, the data that reside in the higher portion of the first register and corresponds to the data in the second register should also be modified. However, with the use of a normal command, the content of the bank register (corresponding to the second register) is transferred to the lower portion of the general-purpose register (corresponding to the first register), thus requiring a shift operation in the general-purpose register after the data is transferred to the lower portion. Hence, two commands are required. It is desirable that the same process be executed using one command. For example, by connecting the input points of the higher 16-bit portion of the first register to the output points of the second register, and by providing a command for reading the data in the first register and adding 0s to the read data, and for transferring the result of addition to the first register, it is possible to have the content of the second register automatically appended to the result of addition and stored in the higher 16-bit portion of the first register.
It is also possible to configure the second register to have an 8-bit size and to provide a constant generator for supplying a specific constant (for example, 0) to

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