Central processing unit architecture with multiple pipelines...

Details Central processing unit architecture with multiple pipelines... Central processing unit architecture with multiple pipelines...

2005-08-10

2009-11-17

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S234000, C712S237000

Reexamination Certificate

active

07620804

ABSTRACT:
A central processing unit (CPU) architecture with enhanced branch execution, being substantially a pipelined CPU with multiple pipelines, each pipeline having a plurality of stages, by which all instructions relating directly to a branch instruction of a code executed by the pipelined CPU are being fetched respectively by each corresponding pipeline for enabling the code to be executed without stall so that the number of cycles required to execute the code can be reduced effectively. Moreover, the multiple pipelines can save more cycles when the number of stages in one pipeline is large.

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