Electrical computers and digital processing systems: support – Multiple computer communication using cryptography – Protection at a particular protocol layer
Reexamination Certificate
1998-01-09
2001-09-04
Pan, Daniel H. (Department: 2171)
Electrical computers and digital processing systems: support
Multiple computer communication using cryptography
Protection at a particular protocol layer
C713S152000, C380S028000, C380S237000
Reexamination Certificate
active
06286101
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a central processing unit and microcomputer system preferably applied to cryptography, and particularly to an improved central processing unit and microcomputer capable of easily implementing an extended operational function other than predetermined ones in the central processing unit.
2. Description of Related Art
FIG. 12
is a block diagram showing a configuration of a conventional microcomputer system. In
FIG. 12
, the reference numeral
1
designates a memory for storing programs a central processing unit (CPU) executes,
2
designates the CPU executing instructions of the programs step by step,
3
designates an external operation unit including a plurality of logic circuits interconnected in accordance with a setting of a user, and
4
designates an external bus line interconnecting the three components
1
-
3
to exchange information.
The reference numeral
5
designates a controller for decoding the instructions and for controlling the operation of the microcomputer system in its entirety, and
6
designates an operation block which includes a register file the operational instructions can directly refer to, and carries out predetermined operations based on two input data including input data set in the register file. Thus, the central processing unit is constructed.
Here, the term “register file the operational instructions can directly refer to” refers to a register file that can be used in such a manner that in “ADD A, B, C” operation, for example, in which data A and B is added and its result is stored in C, an address in the register file is described as A, and its content can used as the actual data of the addition.
Next, the operation of the conventional system will be described.
First, the controller
5
of the central processing unit
2
reads an instruction from the memory
1
, decodes the instruction, and carries out control in accordance with it.
For example, when the instruction is an add operation of two data in the operation block
6
, and stores its result in the register file in the operation block
6
, the controller
5
supplies the operation block
6
with data through the external bus line
4
, and outputs a control signal to store the resultant sum in the register file. Thus, the operation block
6
adds to the data set in the register file the data supplied through the external bus line
4
, and stores the sum in the register file.
Likewise, when having the external operation unit
3
execute data processing, the controller
5
supplies the external operation unit
3
with data and a control signal to execute the operation through the external bus line
4
. The external operation unit
3
, in response to this, carries out operation between the supplied data and data preset therein.
The controller
5
continues to perform such control based on the instructions of the program step by step, so that the microcomputer achieves the intended operation.
With such a configuration, the conventional microcomputer must use the external operation unit
3
when it carries out an extended operation other than operations predefined by the CPU, which results in some problems which will be described below.
Incidentally, a common conventional CPU is only provided with logic operations such as logical OR or logical AND over the entire bits of data, or arithmetic operations such as addition or subtraction over the entire bits of data. Even higher rank CPUs include only such operations as multiplication or division between two data at most.
Next, the problems involved in the conventional microcomputer system will be described.
To provide the external operation unit
3
, a system designer, after completing the logic design of the operational functions to be implemented by the external operation unit
3
, selects optimal gate arrays or field programmable gate arrays, and makes an electric, physical design such as bus connection between the external operation unit
3
and the central processing unit
2
. Thus, providing the conventional microcomputer system with an extended operation results in an increase in development load of a user, prolongation of a development time, and an increase in development cost due to increase in the number of components and to development of a logic unit specific to the system.
Furthermore, even if the extended operation can be implemented at the cost of these factors, a problem arises in that it can prolong the cycle time and hence would degrade the performance of the system. This is because it is necessary for the CPU to consider, in addition to the instruction cycle of the operation, a read cycle to fetch the operation result held by the external operation unit
3
in order to have the external operation unit
3
carry out the operation and to use that result, which will require an overhead time.
On the other hand, to implement a flexible system design by way of software using common instructions, a microcomputer operating at a higher clock frequency is required. This will demand higher cost components and increase in power consumption.
In particular, it is necessary for a microcomputer system requiring cryptographic protection to execute part of the operation involved in cryptography with the external operation unit
3
. This is because the cryptograph encrypted entirely using software can be rather easily decrypted, and hence has a problem in confidentiality. As a result, it has become essential to develop the external operation unit
3
, which causes problems such as prolongation of development time and an increase in the development cost.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a central processing unit and a microcomputer which can easily implement extended functions such as cryptographic operation without any additional hardware like an auxiliary operation unit.
Another object of the present invention is to provide a microcomputer system which is easily developed and can implement highly confidential cryptographic protection.
According to a first aspect of the present invention, there is provided a central processing unit comprising: an operation block including a register file an operational instruction can directly refer to, the operation block performing an operation on two or more input data including data set in the register file; a controller for setting, to the operation block, predetermined data in response to the operational instruction, and for carrying out control with reference to an operation result of the operation block; and an operation unit, included in the operation block, for achieving a set operation, the operation unit having a facility which provides users with capability of setting the operation of the operation unit.
Here, the operation block may comprise only the operation unit as an operational facility.
The operation unit may comprise a logic circuit for performing a plurality of operations on the input data, and an extended operational function setting register for selecting one of the plurality of operations of the logic circuit.
The logic circuit may comprise a plurality of logic segments, and may change connection of the logic segments in accordance with a setting of the extended operational function setting register.
The extended operational function setting register may be a write only register which prevents its data from being read.
The operation unit may comprise a logic circuit for performing a predetermined logic operation, and an internal connection switching circuit, interposed between a data input terminal of the operation unit and an input terminal of the logic circuit, for switching interconnection between the two input terminals.
The central processing unit may further comprise an extended set function eliminating circuit for eliminating contents of the extended operational function setting register when the controller does not supply, within a predetermined interval, the extended opera
Burns Doane , Swecker, Mathis LLP
Chen Te Yu
Mitsubishi Denki & Kabushiki Kaisha
Pan Daniel H.
LandOfFree
Central processing unit and microcomputer system having an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Central processing unit and microcomputer system having an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Central processing unit and microcomputer system having an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2440100