Central processing unit adapted for pipeline process

Details Central processing unit adapted for pipeline process Central processing unit adapted for pipeline process

1997-10-23

2000-03-28

Treat, William M.

Electrical computers and digital processing systems: processing

Instruction decoding

Predecoding of instruction component

712207, 711220, G06F 932

Patent

active

06044455&

ABSTRACT:
A central processing unit includes an adder dedicated to address calculation provided separately from an ALU, a first address data route connected to a program counter and a stack pointer register, a second address data route connected to a prefetch que, a predecoder for determining whether an instruction to be executed calls for an addressing mode whereby a value in the program counter or the SP register is added to an immediate address in an instruction code. With this arrangement, if the addressing mode is called for, address calculation by the adder is performed concurrently with computation using an operand for another instruction, in accordance with a control signal output by the predecoder.

REFERENCES:
patent: 4133028 (1979-01-01), Bernstein
patent: 4538223 (1985-08-01), Vahlstrom et al.
patent: 5357620 (1994-10-01), Suzuki
patent: 5522053 (1996-05-01), Poshida et al.

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