Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-05
2001-08-07
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S303000, C257S532000, C361S306100
Reexamination Certificate
active
06271557
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor memories and more particularly, to trench capacitors having a center node to increase capacitive area and reduce charge leakage.
2. Description of the Related Art
Trench capacitor cells in dynamic random access memories (DRAMs) are commonly formed in a substrate. Trench capacitor cells include a trench having a storage node formed therein. The storage node acts as a first electrode to the trench capacitor. A buried plate is formed externally to the trench to form an outer plate of the trench capacitor, that is, the second electrode of the capacitor. The buried plate is formed by doping the silicon surrounding the etched trench which is then coated with a node dielectric and filled with a conductive material serving as the storage node or inner plate of the capacitor. The inner plate (or storage node) stores the signal charge and is connected to the drain of a transfer transistor switched by a wordline.
Referring to
FIG. 1
, the structure of a conventional trench capacitor is schematically shown. A bitline BL is connected to a source of a transfer transistor
12
. A gate of transistor
12
is connected to a wordline WL. A drain of transistor is connected to a storage node
14
disposed withing a trench. A buried plate
16
is disposed in operative relationship to storage node
14
to form a trench capacitor. The trench capacitor is charged and discharged using bitline BL and wordline WL.
As smaller feature sizes are needed for future generations of trench capacitors, the conventional trench capacitors are pushed to the limits of their capabilities in terms of performance. One primary problem with DRAM designs using deep trench capacitor storage cells is maintaining a high capacity with decreasing feature size and keeping the charge in the deep trench from leaking out of the storage node. The conventional trench capacitors begin to lose capacitive area with smaller feature sizes and are susceptible to current leakage.
Therefore, a need exists for an improved trench capacitor for increasing capacitance and reducing current leakage therefrom.
SUMMARY OF THE INVENTION
A trench capacitor cell, in accordance with the present invention, includes a trench having an outer electrode formed in a substrate adjacent to the trench. A storage node is formed in the trench and capacitively coupled to the outer electrode. A center node is capacitively coupled to the storage node, and the storage node surrounds the center node within the trench. The center node includes a portion extending from the trench for connecting to a potential to provide charge retention in the storage node during operation.
In alternate embodiments, the trench capacitor cell preferably includes a transfer transistor coupled to the storage node for charging and discharging the trench capacitor. The portion of the center node extending from the trench may include a connection to a wordline, and the wordline may be an active wordline for the trench capacitor cell or a passing wordline. The center node to the storage node capacitance may be between about 0.5 fF to about 30 fF and preferably about 5fF, although other values may be employed depending on specific cell designs. The potential may be controlled by a control circuit coupled to the center node for adjusting the potential to maintain charge retention in the storage node, or the potential may be a constant potential. The control circuit may vary the potential to the center node in accordance with operations performed on the trench capacitor cell.
Another trench capacitor cell, in accordance with the present invention, includes a trench having an outer electrode formed in a substrate adjacent to the trench. A storage node is formed in the trench and is capacitively coupled to the outer electrode. The storage node is connected to a transfer transistor which enables the storage node to be charged and discharged. A center node is capacitively coupled to the storage node, and the storage node surrounds the center node within the trench. The center node includes a portion which connects to a gate of the transfer transistor to provide charge retention in the storage node during operation.
A bitline is preferably coupled to the transfer transistor for charging and discharging the trench capacitor. The gate of the transfer transistor may include a wordline. The wordline may be an active wordline for the trench capacitor cell. The center node to the storage node capacitance may be between about 0.5 fF to about 30fF, and preferably about 5fF.
Another trench capacitor cell, in accordance with the present invention, includes a trench having an outer electrode formed in a substrate adjacent to the trench. A storage node is formed in the trench and capacitively coupled to the outer electrode. The storage node is connected to a transfer transistor which enables the storage node to be charged and discharged. A center node is capacitively coupled to the storage node, and the storage node surrounds the center node within the trench. The center node includes a portion connecting to a passing wordline to provide charge retention in the storage node during operation.
In alternate embodiments, the transfer transistor may include a gate connected to an active wordline, and the active wordline and the passive wordline may be activated concurrently. The concurrent activation of the active wordline and the passive wordline may be provided by disposing one bitline of each bitline pair on opposite sides of a sense amplifier such that the pair of bitlines are not adjacently disposed.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 4877750 (1989-10-01), Okumura
patent: 4905065 (1990-02-01), Selcuk et al.
patent: 5012308 (1991-04-01), Hieda
patent: 5066609 (1991-11-01), Yamamoto et al.
patent: 5168336 (1992-12-01), Mikoshiba
patent: 5354701 (1994-10-01), Chao
N. C. C. Lu, Advanced Cell Structures for Dynamic RAMs, Jan. 1989, IEEE Circuits and Devices Magazine, pp. 27-36.
Achammer Thomas
Zimmermann Ulrich
Braden Stanton C.
Eckert II George C.
Infineon - Technologies AG
Lee Eddie
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