Cells of nonvolatile memory device with high inter-layer...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S315000, C257S296000

Reexamination Certificate

active

06903406

ABSTRACT:
This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

REFERENCES:
patent: 5268320 (1993-12-01), Holler et al.
patent: 5886368 (1999-03-01), Forbes et al.
patent: 5998264 (1999-12-01), Wu
patent: 6171909 (2001-01-01), Ding et al.
patent: 6235589 (2001-05-01), Meguro
patent: 6441421 (2002-08-01), Clevenger et al.
patent: 6444592 (2002-09-01), Ballantine et al.
patent: 08-172174 (1996-02-01), None
patent: 1020010066386 (2001-07-01), None
Article entitled “A Novel CMOS Compatible Stacked Floating Gate Device Using TiN as a Control Gate” from 1997 Symposium on VLSI Technology Digest of Technical Papers.
Article entitled “Ultra-Thin Ta2O5/SiO2Gate Insulator with TiN Gate Technology for 0.1 μm MOSFETs” from 1997 Symposium on VLSI Technology Digest of Technical Papers.
English language abstract of Korea Publication No. 1020010066386.
English language abstract of Japanese Publication No. 08-172174.

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