Cell structure with buried capacitor for soft error rate...

Details Cell structure with buried capacitor for soft error rate... Cell structure with buried capacitor for soft error rate...

2011-01-04

2011-01-04

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S149000, C365S145000

Reexamination Certificate

active

07864561

ABSTRACT:
A semiconductor memory device with an improved protection against soft errors includes a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor electrically couples the data storage node to a predefined voltage and a second capacitor electrically couples the data bar storage node to the predefined voltage. Each one of the first and second capacitors includes a top conductive electrode overlying a bottom contact electrode with a dielectric layer disposed in-between. The bottom contact electrode overlays at least two different active regions forming the data and data bar storage nodes.

REFERENCES:
patent: 6831852 (2004-12-01), Ishigaki et al.
patent: 2003/0123276 (2003-07-01), Yokozeki
patent: 2004/0076071 (2004-04-01), Liaw
patent: 2005/0141265 (2005-06-01), Yokoyama

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