Cell structure of ferroelectric memory device

Details Cell structure of ferroelectric memory device Cell structure of ferroelectric memory device

1999-10-25

2001-04-10

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189090, C365S203000

Reexamination Certificate

active

06215691

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory device, and in particular to an improved cell structure of a ferroelectric memory device which can prevent a data loss.
2. Description of the Background Art
As illustrated in
FIG. 1
, a conventional ferroelectric memory cell includes a ferroelectric capacitor X
0
or X
1
operated as a charge storing unit, and a MOS transistor NO or N
1
for sense and read operations. Read and write operations are performed by driving a plate line PL. Here, the MOS transistor N
0
is turned on according to an enable state of a word line WL
0
, and the MOS transistor N
1
is turned on according to an enable state of a word line WL
1
.
That is, in the conventional ferroelectric memory cell, as shown in
FIG. 2
, a bit line precharge signal BLP is maintained at a high H level at an initial stage, and thus MOS transistors N
2
, N
3
are turned on. As a result, a pair of bit lines BL, /BL become a ground voltage level. Thereafter, the bit line precharge signal BLP is transited from high H to low L, and thus the MOS transistors N
2
, N
3
are turned off. Accordingly, the pair of bit lines BL, /BL are precharged to the ground voltage level. As the word line WL
0
of the two word lines W
0
, W
1
is selected and enabled at a voltage level of “Vcc+Vt”, the MOS transistor N
0
is turned on. When the plate line PL is transited from low to high, the bit line BL becomes a high level, and the bit line bar /BL becomes a low level. When the plate line PL become a high level, the bit line BL is increased to a voltage to be compared with a reference voltage, and thus a sense amplifier
14
senses that data “1” is currently stored. Thereafter, when the bit line precharge signal BLP is transited from low to high, the pair of bit lines BL, /BL become the ground voltage level.
In the conventional ferroelectric memory cell, the plate line PL consists of platinum Pt. A dielectric constant of the platinum is great, and thus a parasitic capacitance is also great. Accordingly, as depicted in
FIG. 2
, until the plate line PL is driven from low to high after the word line WL
0
is selected, a predetermined delay time tl is consumed, thereby lowering a speed in reading or writing a data.
As illustrated in
FIG. 3
, in order to solve the delay time of the circuit, there has been suggested a circuit for removing a time delayed in driving the plate line PL by applying “Vcc/
2
” to the plate line PL.
That is, the circuit as shown in
FIG. 3
further includes MOS transistors N
4
. N
5
connected in series between the pair of bit lines BL, /BL, turned on according to a bit line half Vcc precharge signal BCG, and converting the pair of bit lines BL, /BL to a Vcc/
2
state, and applies Vcc/
2
to the plate line PL, differently from the circuit as shown in FIG.
1
.
In the case of the circuit as shown in
FIG. 3
, as illustrated in
FIG. 4
, while the data sensing operation is performed on the selected word line WL
0
at a high speed, the bit line half Vcc precharge signal BCG is maintained at a low level. When the data sensing operation is finished on the word line WL
0
, the bit line half Vcc precharge signal BCG is transited from low to high, thereby turning on the MOS transistors N
4
, N
5
. Accordingly, the pair of bit lines BL, /BL become a Vcc/
2
state, and the data is restored. Thereafter, when the bit line precharge signal BLP is transited from low to high, the MOS transistors N
2
, N
3
are turned on, and thus the pair of bit lines BL, /BL become the ground voltage level.
However, in the operation of the circuit as shown in
FIG. 3
, when the selected word line WL
0
is transited from high to low, the MOS transistor N
0
is turned off. At this time, the Vcc/
2
voltage is being applied to the plate line PL, and thus an upper electrode (a portion connected to a source of the MOS transistor N
0
) of the ferroelectric capacitor X
0
is floated. Accordingly, a leakage is generated at the upper electrode of the ferroelectric capacitor X
0
, and thus the data are lost.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a cell structure of a ferroelectric memory device which can prevent a data from being lost, and improve a data read/write speed.
In order to achieve the above-described object of the present invention, there is provided a cell structure of a ferroelectric memory device including: first and second MOS transistors connected in series between two bit lines, and performing a switching operation according to an enable state of a word line; a third MOS transistor connected between the first and second MOS transistors and a plate line, and engaged with the first and second MOS transistors according to an enable state of the word line; and first and second ferroelectric capacitors connected between the first MOS transistor and the third MOS transistor, and between the second MOS transistor and the third MOS transistor, respectively, and storing data in accordance with a switching state of the first to third MOS transistors.


REFERENCES:
patent: 5917746 (1999-06-01), Seyyedy
patent: 6034884 (1999-06-01), Jung

Affiliated with

Also associated with

Rating

Cell structure of ferroelectric memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cell structure of ferroelectric memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cell structure of ferroelectric memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2541580