Cell refresh circuit of memory device

Details Cell refresh circuit of memory device Cell refresh circuit of memory device

1998-02-13

2000-06-27

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

365226, 365236, 365233, G11C 700

Patent

active

060814721

ABSTRACT:
A cell refresh circuit of a memory device is provided that prevents deterioration in EPROM programmed data. The cell refresh circuit compensates for the loss of programmed data by reprogramming the programmed data in the EPROM after a predetermined time. The cell refresh circuit can be used with a memory device that includes a memory block that stores an executable program, data or the like and a sense amplifier that inputs and outputs data with respect to the memory block. The cell refresh circuit includes a power input unit applies a program voltage to the memory block when a program mode signal is enabled in a program mode, a source voltage to the memory block in normal operations and a pumping voltage to the memory block when a reprogram mode signal is enabled. Read/write controllers respectively applies a ROM read enable signal and ROM write enable signal to the sense amplifier. An address selector selects an externally applied address in a user mode and an internally generated address during a clock signal in a reprogramming mode and outputs the selected address to the memory block. A clock signal supply unit outputs a clock signal to the address selector based on a user mode signal, and a count controller determines the predetermined time and outputs the count enable signal to the address selector based on the user mode signal.

REFERENCES:
patent: 5430877 (1995-07-01), Naylor
patent: 5499213 (1996-03-01), Niimi et al.
patent: 5867438 (1999-02-01), Nomura et al.
patent: 5875143 (1999-02-01), Ben-Zvi

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