Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-10-17
2001-01-30
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06182271
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of and an apparatus for placement, upon designing of an integrated circuit (LSI, VLSI, ASIC or the like) having a plurality of routing layers of, for example, the gate array, of cells on a chip in a situation wherein a wire has already routed prior to such placement of cells such as a bulk power supply or a clock signal are present as well as a storage medium on which a cell placement program is stored.
2. Description of the Related Art
As a most representative one of integrated circuits such as, for example, application specific integrated circuits (ASICs), a gate array of the full area device type having no region for exclusive use for routing is known. In order to produce a gate array, a master wafer for which a step of production of transistors has completed and in which basic cells each formed from a plurality of transistors are placed in gratings is prepared in advance, and the connection of routing of a metal is changed so as to realize a desired. function.
A gate array produced in this manner usually has a plurality of routing layers (for example, three layers), and a wire such as a bulk power supply or clock a signal is sometimes routed already on some of those layers prior to placement of cells.
FIG. 13
shows in plan view an example wherein bulk power supply wires (Vdd and Vss)
1
are routed already. Further, an enlarged view of a XIV portion in
FIG. 13
is shown in FIG.
14
. It is to be noted that the size of one grating shown in
FIG. 14
corresponds to the size of a basic cell, and such grating is hereinafter referred to as site unit. Cells are placed along frames of site units without fail. If a grating frame along which cells are placed is used as a unit, the cells need not be basic cells.
If a cell
2
is placed, in a situation wherein a bulk power supply wire (already routed wire)
1
is present, at a position at which it overlaps with the bulk power supply wire
1
as viewed on the plane of the chip as seen in
FIG. 14
, if a wiring pattern
3
in the cell
2
and the bulk power supply wire
1
are present in the same routing layer, then they short-circuit to each other.
Therefore, in order to prevent occurrence of such short-circuiting with certainty, it is a conventional countermeasure to produce a cell placement prohibition in advance in a region decided to be passed by any bulk power supply wire
1
so that, when automatic placement of cells
2
is to be performed subsequently, the cells
2
may not be placed in the region at all.
Accordingly, with such a conventional cell placement procedure as described above, even if the routing layer of a bulk power supply wire
1
and the routing layer of the wiring pattern
3
in a cell
2
are different from each other and no short-circuiting actually occurs between them, it is quite impossible to place the cell
2
at a position at which it overlaps with the bulk power supply wire
1
as viewed on the plane of the chip.
In short, since placement of a cell
2
in a region (already routed region such as a bulk power supply wire
1
) in which it is actually possible to place a cell
2
is prohibited completely, the area which can be used for placement of cells
2
is remarkably smaller than the actual size of a base bulk.
In designing of an integrated circuit such as an LSI, a VLSI or an ASIC, it is necessary to place cells and route between them within a limited area so that specifications or electric characteristics of a circuit may be satisfied. Particularly in recent years, an increase in density and function is required, and it is important that cells are placed efficiently on a single chip.
Thus, it is desired that placement of a cell
2
in a region in which a cell
2
can be placed be not prohibited and the region be utilized effectively so as to place cells as many as possible.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a cell placement method and apparatus for an integrated circuit wherein a placement region for cells is assured to place cells as many as possible to be placed efficiently on a single chip thereby to allow the design of an integrated circuit having a high density and a large number of functions.
In order to attain the object described above, according to an aspect of the present invention, there is provided a cell placement method for an integrated circuit for placing cells in a situation wherein an already routed wire routed prior to the placement of the cells is present in order to design an integrated circuit having a plurality of routing layers, comprising the step of permitting placement of each of the cells at a position at which the cell overlaps with the already routed wire unless a wiring pattern in the cell and the already routed wire overlap with each other in a same routing layer.
According to another aspect of the present invention, there is provided a cell placement apparatus for an integrated circuit for placing cells in a state in which an already routed wire routed prior to the placement of the cells in order to design an integrated circuit having a plurality of routing layers, comprising an already routed wire information storage section for storing a routing state of the already routed wire, a wiring pattern information storage section for storing wiring patterns in the cells, a search section for searching a position of any of the cells based on the routing state of the already routed wire of the already routed wire information storage section and a wiring pattern in the cell of the wiring pattern information storage section, and a placement permission/rejection discrimination section for discriminating, when search for a position of any of the cells is performed by the search section, an overlapping state between the wiring pattern in the cell and the already routed wire at the position of the cell based on the routing state of the already routed wire of the already routed wire information storage section and the wiring pattern in the cell of the wiring pattern information storage section and permitting the placement of the cell at the position when the wiring pattern in the cell and the already routed wire do not overlap with each other in a same routing layer.
According to a further aspect of the present invention, there is provided a storage medium on which a cell placement program for an integrated circuit for placing cells in a state in which an already routed wire routed prior to the placement of the cells in order to design an integrated circuit having a plurality of routing layers by means of a computer is stored, the cell placement program causing the computer to function as search means for searching a position of any of the cells based on a routing state of the already routed wire stored in an already routed wire information storage section and a wiring pattern in the cell stored in a wiring pattern information storage section, and placement permission/rejection discrimination means for discriminating, when search for a position of any of the cells is performed by the search section, an overlapping state between the wiring pattern in the cell and the already routed wire at the position of the cell based on the routing state of the already routed wire of the already routed wire information storage section and the wiring pattern in the cell of the wiring pattern information storage section and permitting the placement of the cell at the position when the wiring pattern in the cell and the already routed wire do not overlap with each other in a same routing layer.
With the cell placement method and apparatus for an integrated circuit and the storage medium on which a cell placement program for an integrated circuit is stored described above, since routing layers which are not used by an already routed wire such as a bulk power supply wire or a clock signal wire are recognized and cells which use only such routing layers can be placed at positions at which they are overlapped with the already routed wire, it is possible to utilize a regio
Fujitsu Limited
Kik Phallaka
Lintz Paul R.
Staas & Halsey , LLP
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