Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-10-20
2001-12-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06327694
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a cell placement apparatus and method for use in a layout design following a logic design in a computer aided design automation of LSIs or VLSIs and to a computer readable record medium having a cell placement program stored thereon. More particularly, it is directed to a cell placement apparatus and method for realizing an optimum cell placement with a restricted cell activity ratio of a high-density wiring region on a cell, as well as to a computer readable record medium on which a cell placement program is stored.
2. Description of the Related Arts
In a CAD system for automatically designing large-scale semiconductor integrated circuits such as VLSIs or LSIs with the aid of a computer, a logic design is first carried out for determining AND, OR or other cells and cell-to-cell connections (nets). Cell placement processing is then performed for determining locations of cells on a chip on the basis of a netlist acquired from the logic design. Wiring processing (routing) is finally effected for determining the wiring, that is, how to provide nets between the cells placed on the chip.
Known as the cell placement processing is for example a partitioning based placement algorithm. In the partitioning based placement algorithm, the entire chip is first partitioned into two regions so that all the cells are assigned to the two regions obtained as a result of the partitioning. A criterion for the cell assignment is a cost which is the number of nets connecting the two regions when the cells are assigned to the two regions. The grouping is so made as to minimize the cost. Such cell region partitioning and cell assignment are iterated until the partitioned blocks result in minimum blocks each corresponding to a single cell. In this case, if the cells become dense at one place as a result of the cell placement on the chip, it may be impossible to effect the wiring. Hence, the placement is carried out with a restriction condition of the cell distribution. In order to establish the restriction condition, cell activity ratios &rgr;(
1
) and &rgr;(
2
) of the two regions are first figured out from
&rgr;(
2
)=s
1
/S
1
&rgr;(
2
)=s
2
/S
2
The cells are then grouped so as to meet a restriction condition given as a conditional expression that an absolute value of a difference between the activity ratios of the two regions should be equal to or less than a positive constant &agr;, that is, a restriction condition given as
|(s
1
/S
1
)−(s
2
/S
2
)|≦&agr; (1)
where &agr; is a positive constant.
An appropriate dispersion of the cells are thus achieved by placing the cells so as to fulfill the condition that the difference between the cell activity ratios upon the block partitioning lies within a certain range. Such a restriction condition for the cell activity ratios is called an area restriction.
In typical computer aided cell placement processing, however, all the cells are not newly placed on the chip. For example, clock signal sending cells, RAMs or other cells are already located previous to the automatic cell placement. For this reason, conventional cell placement processing having the area restriction defined as a cell placement restriction condition may suffer from an inconvenience that uneven wiring density may occur in the wiring processing which is carried out after the completion of the cell placement, if there exist already placed cells of which placement locations have been previously determined on the chip, due to nets connecting to the already placed cells. As a result of this, a portion having a higher wiring density must be given a lower cell activity ratio than the other portions upon the cell placement since it requires a larger area for the wiring than the areas required by the other portions. The wiring density could be substantially accurately estimated by an execution of rough wiring. A method is thus conceivable in which the rough wiring is performed at the time of completion of the cell placement with the addition of an operation for removing some cells from a high-density wiring portion. However, in the event of removing the cells from the high-density wiring portion for relocation to the other portions, the cell activity ratio restriction condition for the cell placement processing may collapse, which may result in an overall degradation of the cell placement quality and unfeasible wiring. Another algorithm such as simulated annealing would also be available to perform the operation for removing some cells from a high-density wiring portion for the relocation to the other portions while assuring the cell placement quality. However, this method may need more processing time although the cell placement quality is assured.
An approach to a reduction of the cell activity area in a specific region is a use of a cell placement inhibition region or a floor plan. However, the cell placement inhibition region is provided to entirely inhibit the placement of cells in a region. Therefore, in the event that the cell placement inhibition region is partially provided in a region to reduce the cell activity area, this may possibly induce a more serious inconvenience that the presence of this cell placement inhibition region may impose a size limitation of cells which can be placed therein, impeding the placement of larger cells. The floor plan is used to specify a region in which is arranged a module (macro cell) making up a certain logic. In case of the floor plan, the logic determines a unit to be controlled. This may make it hard to reduce the cell activity area of a high-density wiring region existing in a module by use of the floor plan. It may also be unfeasible for the floor plan to reduce the cell activity area of a high-density wiring region which exists between two modules. That is, both the cell placement inhibition region and the floor plan were conceived for the other objects, with no intention to reduce the cell activity area of a high-density wiring region. Thus, there have arisen deficiencies that existence of already placed cells or other cells on the chip may make the wiring difficult due to the occurrence of high-density portions of both the nets and cells and that the reexecution of the cell placement to avoid this may result in extended processing time.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a cell placement apparatus capable of preventing the wiring from becoming difficult due to an increased wiring density in a specific cell placement region attributable to the already placed cells, etc.
The cell placement apparatus of the present invention comprises a restricted region specifying module, a restricted region managing module and a cell placing module. The restricted region specifying module specifies both a restricted region in which is restricted a cell activity ratio indicative of a ratio of a cell occupied area to a chip surface area and a cell maximum activity ratio &rgr;, e.g., &rgr;=50%, of the restricted region. The restricted region managing module accepts for management the restricted region and the cell maximum activity ratio specified by the restricted region specifying module. The cell placing module places cells in such a manner that the cell activity ratio of the restricted region managed by the restricted region managing module does not exceed the cell maximum activity ratio. In case of the cell placement apparatus of the present invention in this manner, a portion likely to have a higher wiring density on the chip is specified as a restricted region in which the cell activity ratio is restricted while simultaneously specifying the maximum cell activity ratio within the restricted region, whereby cells are arranged in such a manner that the cell activity ratio of the specified restricted region does not exceed the specified maximum cell activity ratio, so that a high wiring density region has a low cell activity ratio so as to ensure secure w
Do Thuan
Fujitsu Limited
Smith Matthew
Staas & Halsey , LLP
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